ZLF645S0P2864G Zilog, ZLF645S0P2864G Datasheet - Page 146

• Manufacturer Part Number: ZLF645S0P2864G
• Description: Microcontrollers (MCU) 64K Flash 512B RAM 28 pin
• Manufacturer: Zilog

Specifications of ZLF645S0P2864G

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 512 KB
• Interface Type: ICP, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIP-28
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details

PS026407-0408
Note:
Fast Stop Mode Recovery
Stop Mode Recovery Interrupt
Stop Mode Recovery Event Sources
to their Power-On Reset defaults. A Stop Mode Recovery restores most registers to their
Power-On Reset defaults. Register bits not reset by a Stop Mode Recovery are highlighted
in grey in the register tables. Register bit SMR[7] is set to 1 instead of reset by a Stop
Mode Recovery.
SMR[5] can be cleared to 0 before entering STOP mode to bypass the default T
timer on Stop Mode Recovery. See
If SMR[5]=0, the Stop Mode Recovery source must be kept active for at least 10 input
clock periods (TpC).
SMR[5] must be set to 1 if using a crystal or resonator clock source. The T
allows the clock source to stabilize before executing instructions.
Software can set register bit SMR4[4] = 1 to enable routing of Stop Mode Recovery events
to IRQ1 and to Port 3, Pin 3. In this configuration, if an IRQ1 interrupt occurs, register bit
P3[3] = 0 indicates that a Stop Mode Recovery event is occurring.
Any Port 2 or Port 3 input pin can be configured to generate a Stop Mode Recovery event,
either individually or in various logical combinations. The ZLF645 MCU provides the
following registers for Stop Mode Recovery source configuration and status:
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A Stop Mode Recovery event occurs if any of the sources defined in the SMR, SMR1,
SMR2, and SMR3 registers are active.
SMR Register—Selects one Port 3, Pin 1–3 pin state or one of three Port 2 pin logical
combinations to generate an event when a defined 0 or 1 level occurs.
SMR1 Register—Configures one or more Port 2 input pins (0–7) to latch the latest
read or write value and generate an event when the pin state changes.
SMR2 Register—Selects one of seven Port 2 and 3 pin logical combinations to
generate an event when a defined 0 or 1 level occurs.
SMR3 Register—Configures one or more Port 3 input pins (0–3) to latch the latest
read or write value and generates an event when the pin state changes.
SMR4 Register—Enables routing of SMR events to IRQ1. Indicates whether port data
has been latched for SMR1 or SMR3 event monitoring, and whether the latch was on
a port read or write.
Voltage Brownout Standby
ZLF645 Series Flash MCUs
Reset/Stop Mode Recovery Status
on page 134.
Product Specification
POR
POR
delay
reset
138