ZLF645S0P2864G Zilog, ZLF645S0P2864G Datasheet - Page 51

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ZLF645S0P2864G

Manufacturer Part Number
ZLF645S0P2864G
Description
Microcontrollers (MCU) 64K Flash 512B RAM 28 pin
Manufacturer
Zilog
Datasheet

Specifications of ZLF645S0P2864G

Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
512 KB
Interface Type
ICP, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Package / Case
PDIP-28
Minimum Operating Temperature
0 C
Lead Free Status / Rohs Status
 Details
PS026407-0408
P orts 00h -04h
C P U C ontrol
R egisters
F 0 h-F F h
05h-E F h
P urpose
G eneral
**
B ank 0
= B ank-Independent A ddress (A lw ays A ccesses B ank 0 )
For 20 and 28 pin parts, the P ort01 and P ort04 locations
becom e available for use as general purpose registers
shadow registers implemented within the RAM memory. This enables the entire 1K or 512
B, depending on the product, of the RAM memory to be used for the stack.
8-bit Stack Addressability
For 8-bit stack addressability, only the SPL register is used for stack addressing and stack
operations that use the stack pointer always address Bank 0, independent of the RP[3:0]
setting. For more details on the stack, refer to Z8
(UM0215).
When in 8-bit stack addressability mode, the Bank 0 register FEh can be used to store user
data. See
**
B anks 1-3
Stack Pointer Register
Figure 13. Register File 8-Bit Banked Address Map
P orts 00h -04h
C P U C ontrol
R egisters
F 0 h-F F h
P urpose
05h-E F h
G eneral
C P U C ontrol
F 0 h-F F h
C P U C ontrol
F 0 h-F F h
**
on page 48.
C P U C ontrol
P eripheral
R egisters
F 0 h-F F h
P urpose
10h-E F h
0 0 h-0 F h
G eneral
B ank D
B ank D
C ontrol
®
LXMC CPU Core User Manual
ZLF645 Series Flash MCUs
Product Specification
C P U C ontrol
P eripheral
R egisters
F 0 h-F F h
10h-E F h
P urpose
0 0 h-0 F h
G eneral
C ontrol
B ank F
B ank F
Register File
43

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