ST72T631K4M1 STMicroelectronics, ST72T631K4M1 Datasheet - Page 58

• Manufacturer Part Number: ST72T631K4M1
• Description: Microcontrollers (MCU) OTP EPROM 16K USB/SC
• Manufacturer: STMicroelectronics

Specifications of ST72T631K4M1

• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST7263
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
5.5.4.3 Receiver
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the CR1 reg-
ister.
Character reception
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
DR register consists of a buffer (RDR) between
the internal bus and the received shift register (see
Figure 1).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the BRR reg-
– Set the RE bit to enable the receiverto begin
When a character is received:
– The RDRF bit is set. It indicates that the content
– An interrupt is generated if the RIE bit is set and
– The error flags can be set if a frame error, noise
Clearing the RDRF bit is performed by the following
software sequence done by:
1. An access to the SR register
2. A read to the DR register.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
Break Character
When a break character is received, the SCI han-
dles it as a framing error.
Idle Character
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CC register.
58/109
ister.
searching for a start bit.
of the shift register is transferred to the RDR.
the I bit is cleared in the CC register.
or an overrun error has been detected during re-
ception.
Overrun Error
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
When a overrun error occurs:
– The OR bit is set.
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
The OR bit is reset by an access to the SR register
followed by a DR register read operation.
Noise Error
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– Data is transferred from the Shift register to the
– No interrupt is generated. However this bit rises
The NF bit is reset by a SR register read operation
followed by a DR register read operation.
Framing Error
A framing error is detected when:
– The stop bit is not recognized on reception at the
– A break is received.
When the framing error is detected:
– The FE bit is set by hardware
– Data is transferred from the Shift register to the
– No interrupt is generated. However this bit rises
The FE bit is reset by a SR register read operation
followed by a DR register read operation.
the I bit is cleared in the CC register.
DR register.
at the same time as the RDRF bit which itself
generates an interrupt.
expected time, following either a de-synchroni-
zation or excessive noise.
DR register.
at the same time as the RDRF bit which itself
generates an interrupt.