LPC11C22FBD48/301,151 NXP Semiconductors, LPC11C22FBD48/301,151 Datasheet - Page 26
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LPC11C22FBD48/301,151
Manufacturer Part Number
LPC11C22FBD48/301,151
Description
Microcontrollers (MCU) CAN Transceiver MCU 16K Flash
Manufacturer
NXP Semiconductors
Datasheet
1.LPC11C22FBD48301151.pdf
(62 pages)
Specifications of LPC11C22FBD48/301,151
Processor Series
LPC11Cx2
Core
ARM Cortex-M0
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
OM13012,598
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Details
Other names
935294284151
NXP Semiconductors
LPC11CX2_CX4
Product data sheet
CAUTION
7.17.4 Code security (Code Read Protection - CRP)
7.17.5 Bootloader
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
This feature of the LPC11Cx2/Cx4 allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC11Cx user manual.
There are three levels of Code Read Protection:
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11Cx user manual.
The bootloader controls initial operation after reset and also provides the means to
program the flash memory. This could be initial programming of a blank device, erasure
and re-programming of a previously programmed device, or programming of the flash
memory by the application program in a running system.
The bootloader code is executed every time the part is reset or powered up. The loader
can either execute the user application code or the ISP command handler via UART or
C_CAN. A LOW level during reset applied to the PIO0_1 pin is considered as an external
hardware request to start the ISP command handler. The state of PIO0_3 at reset
determines whether the UART (PIO0_3 HIGH) or the C_CAN (PIO0_3 LOW) interface will
be used.
1. CRP1 disables access to the chip via the SWD and allows partial flash update
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to the chip
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
update using a reduced set of the ISP commands.
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the UART.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 June 2011
32-bit ARM Cortex-M0 microcontroller
LPC11Cx2/Cx4
© NXP B.V. 2011. All rights reserved.
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