P89LPC922FDH NXP Semiconductors, P89LPC922FDH Datasheet - Page 14

• Manufacturer Part Number: P89LPC922FDH
• Description: MCU 8-Bit 89LP 80C51 CISC 8KB Flash 2.5V/3.3V 20-Pin TSSOP Tube
• Manufacturer: NXP Semiconductors

Specifications of P89LPC922FDH

• Package: 20TSSOP
• Device Core: 80C51
• Family Name: 89LP
• Maximum Speed: 18 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 18
• Interface Type: I2C/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 2

Philips Semiconductors
8. Functional description
9397 750 14469
Product data
8.2.1 Clock definitions
8.2.2 CPU clock (OSCCLK)
8.2.3 Low speed oscillator option
8.2.4 Medium speed oscillator option
8.2.5 High speed oscillator option
8.1 Enhanced CPU
8.2 Clocks
Remark: Please refer to the P89LPC920/921/922/9221 User’s Manual for a more
detailed functional description.
The P89LPC920/921/922/9221 uses an enhanced 80C51 CPU which runs at 6 times
the speed of standard 80C51 devices. A machine cycle consists of two CPU clock
cycles, and most instructions execute in one or two machine cycles.
The P89LPC920/921/922/9221 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see
(see
Note: f
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
The P89LPC920/921/922/9221 provides several user-selectable oscillator options in
generating the CPU clock. This allows optimization for a range of needs from high
precision to lowest possible cost. These options are configured when the FLASH is
programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an
oscillator using an external crystal, or an external clock source. The crystal oscillator
can be optimized for low, medium, or high frequency crystals covering a range from
20 kHz to 12 MHz.
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until V
reached its specified level. When system power is removed V
Section 8.7 “CPU Clock (CCLK) modification: DIVM
osc
is defined as the OSCCLK frequency.
Rev. 08 — 15 December 2004
Figure
5) and can also be optionally divided to a slower frequency
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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