P89LPC922FDH NXP Semiconductors, P89LPC922FDH Datasheet - Page 19

• Manufacturer Part Number: P89LPC922FDH
• Description: MCU 8-Bit 89LP 80C51 CISC 8KB Flash 2.5V/3.3V 20-Pin TSSOP Tube
• Manufacturer: NXP Semiconductors

Specifications of P89LPC922FDH

• Package: 20TSSOP
• Device Core: 80C51
• Family Name: 89LP
• Maximum Speed: 18 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 18
• Interface Type: I2C/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 2

Philips Semiconductors
9397 750 14469
Product data
Fig 6. Interrupt sources, interrupt enables, and power-down wake-up sources.
(RTCCON.1)
WDOVF
ERTC
RTCF
8.12.1 Port configurations
8.12 I/O ports
The P89LPC920/921/922/9221 has three I/O ports: Port 0, Port 1, and Port 3. Ports 0
and 1 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available
depend upon the clock and reset options chosen, as shown in
Table 6:
[1]
All but three I/O port pins on the P89LPC920/921/922/9221 may be configured by
software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional
(standard 80C51 port outputs), push-pull, open drain, and input-only. Two
configuration registers for each port select the output type for each port pin.
P1.5 (RST) can only be an input and cannot be configured.
Clock source
On-chip oscillator or
watchdog oscillator
External clock input
Low/medium/high
speed oscillator
(external crystal or
resonator)
Required for operation above 12 MHz.
EA (IE0.7)
TI & RI/RI
EWDRT
ES/ESR
CMF2
CMF1
EKBI
KBIF
EI2C
BOF
EBO
EX0
EX1
EST
ET0
ET1
TF0
TF1
IE0
IE1
EC
SI
Number of I/O pins available
TI
Rev. 08 — 15 December 2004
Reset option
No external reset (except during power-up)
External RST pin supported
No external reset (except during power-up)
External RST pin supported
No external reset (except during power-up)
External RST pin supported
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
[1]
[1]
[1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
002aaa418
Number of I/O pins
(20-pin package)
18
17
17
16
16
15
INTERRUPT
TO CPU
WAKE-UP
(IF IN POWER-DOWN)
Table
6.
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