STA013$ STMicroelectronics, STA013$ Datasheet - Page 10

• Manufacturer Part Number: STA013$
• Description: DECODER AUDIO MPEG 2.5 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA013$

• Applications: Sound Cards, Players, Recorders
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 1
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Sampling Rate: 48kSPS
• Interface Type: I2C, Serial
• Supply Voltage Range: 2.4V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Compliant

STA013 - STA013B - STA013T
3.1.2 - Stop condition
STOP is identified by low to high transition of the
data bus SDA signal while the clock signal SCL is
stable in the high state. A STOP condition termi-
nates communications between STA013 and the
bus master.
3.1.3 - Acknowledge bit
An acknowledge bit is used to indicate a success-
ful data transfer. The bus transmitter, either mas-
ter or slave, releases the SDA bus after sending
8 bit of data.
During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits
of data.
3.1.4 - Data input
During the data input the STA013 samples the
SDA signal on the rising edge of the clock SCL.
For correct device operation the SDA signal has
to be stable during the rising edge of the clock
and the data can change only when the SCL line
is low.
3.2 - DEVICE ADDRESSING
To start communication between the master and
the STA013, the master must initiate with a start
condition. Following this, the master sends onto
the SDA line 8 bits (MSB first) corresponding to
the device select address and read or write
mode.
Figure 10. Write Mode Sequence
Figure 11. Read Mode Sequence
10/38
SEQUENTIAL
SEQUENTIAL
CURRENT
ADDRESS
ADDRESS
CURRENT
RANDOM
RANDOM
READ
READ
READ
READ
START
START
START
START
MULTIBYTE
WRITE
WRITE
BYTE
DEV-ADDR
DEV-ADDR
DEV-ADDR
DEV-ADDR
START
START
HIGH
RW=
RW
RW
RW
ACK
ACK
ACK
ACK
DEV-ADDR
DEV-ADDR
SUB-ADDR
SUB-ADDR
DATA
DATA
RW
RW
ACK
ACK
NO ACK
ACK
ACK
ACK
START
START
SUB-ADDR
SUB-ADDR
STOP
DATA
DEV-ADDR
DEV-ADDR
ACK
ACK
RW
RW
The 7 most significant bits are the device address
identifier, corresponding to the I
For the STA013 these are fixed as 1000011.
The 8th bit (LSB) is the read or write operation
RW, this bit is set to 1 in read mode and 0 for
write mode. After a START condition the STA013
identifies on the bus the device address and, if a
match is found, it acknowledges the identification
on SDA bus during the 9th bit time. The following
byte after the device identification byte is the in-
ternal space address.
3.3 - WRITE OPERATION (see fig. 10)
Following a START condition the master sends a
device select code with the RW bit set to 0.
The STA013 acknowledges this and waits for the
byte of internal address.
After receiving the internal bytes address the
STA013 again responds with an acknowledge.
3.3.1 - Byte write
In the byte write mode the master sends one data
byte, this is acknowledged by STA013. The mas-
ter then terminates the transfer by generating a
STOP condition.
3.3.2 - Multibyte write
The multibyte write mode can start from any inter-
nal address. The transfer is terminated by the
master generating a STOP condition.
ACK
ACK
ACK
DATA IN
DATA IN
DATA
DATA
DATA
ACK
ACK
NO ACK
NO ACK
STOP
ACK
D98AU825B
STOP
STOP
DATA
DATA IN
D98AU826A
ACK
ACK
2
C bus definition.
DATA
STOP
NO ACK
STOP