STA013$ STMicroelectronics, STA013$ Datasheet - Page 22

• Manufacturer Part Number: STA013$
• Description: DECODER AUDIO MPEG 2.5 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA013$

• Applications: Sound Cards, Players, Recorders
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 1
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Sampling Rate: 48kSPS
• Interface Type: I2C, Serial
• Supply Voltage Range: 2.4V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Compliant

STA013 - STA013B - STA013T
PCMCROSS
Address: 0x56
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The default configuration for this register is ’0x00’.
ANCILLARY DATA BUFFER
Address: 0x59 - 0x5D
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
STA013 can extract max 56 bytes/MPEG frame.
To know the number of A.D. bits available every
MPEG frame, the ANCCOUNT_L and ANC-
COUNT_H registers (0x41 and 0x42) have to be
read.
The buffer dimension is 5 bytes, written by
STA013 core in sequential order. The timing in-
formation to read the buffer can be obtained by
reading the FRAME_CNT registers (0x67 - 0x69).
To fill up the buffer with a new 5-bytes slot, the
STA013 waits until a CMD_INTERRUPT register
is written by the master.
MFSDF (X)
Address: 0x61
Type: R/W
Software Reset: 0x07
Hardware Reset: 0x07
The register contains the values for PLL X divider
(see Fig. 7).
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MSB
MSB
b7
b7
X
X
X
X
X
b6
X
b6
X
X
X
X
b5
X
b5
X
X
X
X
M4
b4
b4
X
X
X
X
M3
b3
b3
X
X
X
X
M2
b2
b2
X
X
X
X
M1
b1
b1
LSB
0
1
1
0
M0
b0
LSB
b0
0
1
0
1
The value is changed by the internal STA013
Core, to set the clocks frequencies, according to
the incoming bitstream. This value can be even
set by the user to select the PCM interface con-
figuration.
The VCO output frequency is divided by (X+1).
This register is a reference for 32KHz and 48 KHz
input bitstream.
DAC_CLK_MODE
Address: 0x63
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
This register is used to select the operating mode
for OCLK clock signal.
If it is set to ’1’, the OCLK frequency is fixed, and
it is mantained to the value fixed by the user even
if the sampling frequency of the incoming bit-
stream changes.
It the MODE flag is set to ’0’, the OCLK frequency
changes, and can be set to (512, 384, 256) * Fs.
The default configuration for this mode is 256 *
Fs.
When this mode is selected, the default OCLK
frequency is 12.288 MHz.
MSB
b7
X
Left channel is mapped on the left output.
Right channel is mapped on the Right output
Left channel is duplicated on both Output channels.
Right channel is duplicated on both Output channels
Right and Left channels are toggled
b6
X
b5
X
b4
Description
X
b3
X
b2
X
b1
X
MODE
LSB
b0