STA013$ STMicroelectronics, STA013$ Datasheet - Page 13

• Manufacturer Part Number: STA013$
• Description: DECODER AUDIO MPEG 2.5 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA013$

• Applications: Sound Cards, Players, Recorders
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Audio Codec Type: MP3 Decoder
• No. Of Dacs: 1
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Sampling Rate: 48kSPS
• Interface Type: I2C, Serial
• Supply Voltage Range: 2.4V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Compliant

4.1 - STA013 REGISTERS DESCRIPTION
The STA013 device includes 128 I
this document, only the user-oriented registers
are described. The undocumented registers are
reserved. These registers must never be ac-
cessed (in Read or in Write mode). The Read-
Only registers must never be written.
The following table describes the meaning of the
abbreviations used in the I
tion:
VERSION
Address: 0x00
Type: RO
The VERSION register is read-only and it is used
to identify the IC on the application board.
IDENT
Address: 0x01
Type: RO
Software Reset: 0xAC
Hardware Reset: 0xAC
IDENT is a read-only register and is used to iden-
tify the IC on an application board. IDENT always
has the value "0xAC"
PLLCTL
Address: 0x05
Type: R/W
Software Reset: 0x21
Hardware Reset: 0x21
MSB
MSB
V8
b7
b7
1
Symbol
R/WS
UND
R/W
WO
RO
NA
NC
V7
b6
b6
0
V6
b5
b5
1
V5
b4
b4
Read, Write in specific mode
0
Read and Write
V4
b3
b3
Not Applicable
1
2
No Charge
Comment
Read Only
Write Only
Undefined
C registers descrip-
V3
b2
b2
1
2
C registers. In
V2
b1
b1
0
LSB
LSB
V1
b0
b0
0
UPD_FRAC: when is set to 1, update FRAC in
the switching circuit. It is set to 1 after autoboot.
XTI2OCLK: when is set to 1, use the XTI as input
of the divider X instead of VCO output. It is set to
0 on HW reset.
XTI2DSPCLK: when is to 1, set use the XTI as in-
put of the divider S instead of VCO output. It is
set to 0 on HW reset.
PLLDIS: when set to 1, the VCO output is dis-
abled. It is set to 0 on HW reset.
SYS2OCLK: when is set to 1, the OCLK fre-
quency is equal to the system frequency. It is
useful for testing. It is set to 0 on HW reset.
OCLKEN: when is set to 1, the OCLK pad is en-
able as output pad. It is set to 1 on HW reset.
XTODIS: when is set to 1, the XTO pad is dis-
able. It is set to 0 on HW reset.
XTO_BUF: when this bit is set, the pin nr. 28
(OUT_CLOCK/DATA_REQ) is enabled. It is set
to 0 after autoboot.
PLLCTL (M)
Address: 0x06
Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
PLLCTL (N)
Address: 0x07
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The M and N registers are used to configure the
STA013 PLL by DSP embedded software.
M and N registers are R/W type but they are
completely controlled, on STA013, by DSP soft-
ware.
REQ_POL
Address: 0x0C
Type: R/W
Software Reset: 0x01
Hardware Reset: 0x00
XTO_
MSB
BUF
b7
XTOD
b6
IS
OCLK
STA013 - STA013B - STA013T
EN
b5
SYS2O
CLK
b4
PPLD
b3
IS
XTI2DS
PCLK
b2
XTI2O
CLK
b1
UPD_F
RAC
LSB
13/38
b0