ADV7181BBCPZ Analog Devices Inc, ADV7181BBCPZ Datasheet - Page 61

• Manufacturer Part Number: ADV7181BBCPZ
• Description: IC ENCODER SDTV MULTI 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BBCPZ

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 9bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 54MSPS
• No. Of Input Channels: 6
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER ACCESSES
The MPU can write to or read from all of the ADV7181B’s
registers, except the subaddress register, which is write only.
The subaddress register determines which register the next read
or write operation accesses. All communications with the part
through the bus start with an access to the subaddress register.
Then, a read/write operation is performed from/to the target
address, which then increments to the next address until a stop
command on the bus is performed.
REGISTER PROGRAMMING
The following sections describe the configuration of each
register. The communications register is an 8-bit, write only
register. After the part has been accessed over the bus and a
read/write operation is selected, the subaddress is set up. The
subaddress register determines to/from which register the
operation takes place. Table 82 lists the various operations
under the control of the subaddress register for the control port.
Register Select (SR to SR0)
These bits are set up to point to the required starting address.
Rev. B | Page 61 of 100
I
An I
and is, therefore, distributed over two or more I
example, HSB[11:0].
When a parameter is changed using two or more I
operations, the parameter can hold an invalid value for the time
between the first I
This means that the top bits of the parameter can already hold
the new value while the remaining bits of the parameter still
hold the previous value.
To avoid this problem, the I
updated bits of the parameter in local memory; all bits of the
parameter are updated together once the last register write
operation has completed.
The correct operation of the I
following:
•
•
2
C SEQUENCER
2
All I
written to in order of ascending addresses. For example, for
HSB[10:0], write to Address 0x34 first, followed by 0x35.
No other I
writes for the sequence. For example, for HSB[10:0], write
to Address 0x34 first, immediately followed by 0x35.
C sequencer is used when a parameter exceeds eight bits
2
C registers for the parameter in question must be
2
C taking place between the two (or more) I
2
C completion and the last I
2
C sequencer holds the already
2
C sequencer relies on the
2
C completion.
2
ADV7181B
C registers, for
2
C write
2
C