ADV7181BBCPZ Analog Devices Inc, ADV7181BBCPZ Datasheet - Page 83

• Manufacturer Part Number: ADV7181BBCPZ
• Description: IC ENCODER SDTV MULTI 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BBCPZ

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 9bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 54MSPS
• No. Of Input Channels: 6
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Subaddress
0x51
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
Register
Lock Count
Free Run
Line
Length 1
VBI Info
(Read
Only)
WSS1
(Read Only)
WSS2
(Read Only)
EDTV1
(Read Only)
EDTV2
(Read Only)
EDTV3
(Read Only)
CGMS1
(Read Only)
CGMS2
(Read Only)
CGMS3
(Read Only)
Bit Description
CIL[2:0]. Count-into-lock determines
the number of lines the system must
remain in lock before showing a
locked status.
COL[2:0]. Count-out-of-lock
determines the number of lines the
system must remain out-of-lock
before showing a lost-locked status.
SRLS. Select raw lock signal. Selects
the determination of the locked
status.
FSCLE. Fsc lock enable.
Reserved.
LLC_PAD_SEL[2:0]. Enables manual
selection of clock for LLC1 pin.
Reserved.
WSSD. Screen signaling detected.
CCAPD. Closed caption data.
EDTVD. EDTV sequence.
CGMSD. CGMS sequence.
Reserved.
WSS1[7:0]
Wide screen signaling data.
WSS2[7:0]
Wide screen signaling data.
EDTV1[7:0]
EDTV data register.
EDTV2[7:0]
EDTV data register.
EDTV3[7:0]
EDTV data register.
CGMS1[7:0]
CGMS data register.
CGMS2[7:0]
CGMS data register.
CGMS3[7:0]
CGMS data register.
Rev. B | Page 83 of 100
7 6
0
1
0
x x
x x
x x
x x
x x
x x
x x
x x
x x
0
1
0
1
5
0
0
0
0
1
1
1
1
0
0
x
x
x
x
x
x
x
x
x
4 3
0
0
1
1
0
0
1
1
0
1
x
x
x x
x
x
x
x
x
x
Bits
0
1
0
1
0
1
0
1
0
0
1
x
x
x
x
x
x
x
x
2
0
0
0
0
1
1
1
1
0
0
1
x
x
x
x
x
x
x
x
x
x
1
0
0
1
1
0
0
1
1
0
0
1
x
x
x
x
x
0
0
1
0
1
0
1
0
1
0
0
1
x
x
x
x
x
x
x
x
Comments
1 line of video
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100000 lines of video
1 line of video
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100000 lines of video
Over field with vertical
info
Line-to-line evaluation
Lock status set only by
horizontal lock
Lock status set by
horizontal lock and
subcarrier lock
Set to default
LLC1 (nominal 27 MHz)
selected out on LLC1 pin
LLC2 (nominally 13.5 MHz)
selected out on LLC1 pin
Set to default
No WSS detected
WSS detected
No CCAP signals detected
CCAP sequence detected
No EDTV sequence
detected
EDTV sequence detected
No CGMS transition
detected
CGMS sequence decoded
WSS2[7:6] are
undetermined
EDTV3[7:6] are
undetermined
CGMS3[7:4] are
undetermined
Notes
For 16-bit 4:2:2 out,
OF_SEL[3:0] = 0010.
Read only status
bits.
EDTV3[5] is reserved
for future use.
ADV7181B