ADV7181BBCPZ Analog Devices Inc, ADV7181BBCPZ Datasheet - Page 70

• Manufacturer Part Number: ADV7181BBCPZ
• Description: IC ENCODER SDTV MULTI 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BBCPZ

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 9bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 54MSPS
• No. Of Input Channels: 6
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7181B
Subaddress
0x48
0x49
0x4A
Register
Interrupt
Mask 2
Read/
Write
Register
Access
Page 2
Raw
Status 3
Read Only
Register
Register
Access
Page 2
Interrupt
Status 3
Read Only
Register
Register
Access
Page 2
Bit Description
CCAPD_MSKB.
GEMD_MSKB.
CGMS_CHNGD_MSKB.
WSS_CHNGD_MSKB.
Reserved.
Reserved.
Reserved.
MPU_STIM_INTRQ_MSKB.
SD_OP_50Hz.
SD 60/50Hz frame rate at
output.
SD_V_LOCK.
SD_H_LOCK.
Reserved.
SCM_LOCK.
SECAM Lock.
Reserved.
Reserved.
Reserved.
SD_OP_CHNG_Q.
SD 60/50 Hz frame rate at
input.
SD_V_LOCK_CHNG_Q.
SD_H_LOCK_CHNG_Q.
SD_AD_CHNG_Q.
SD autodetect changed.
SCM_LOCK_CHNG_Q.
SECAM Lock.
PAL_SW_LK_CHNG_Q.
Reserved.
Reserved.
7
0
x
x
Rev. B | Page 70 of 100
6
0
x
x
5
0
x
x
4
0
0
1
0
1
Bit
3
0
1
x
x
2
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
Comments
Masks CCAPD_Q bit
Unmasks CCAPD_Q bit
Masks GEMD_Q bit
Unmasks GEMD_Q bit
Masks CGMS_CHNGD_Q bit
Unmasks CGMS_CHNGD_Q bit
Masks WSS_CHNGD_Q bit
Unmasks WSS_CHNGD_Q bit
Not used
Not used
Not used
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q
bit
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock not
SD vertical sync lock established
SD horizontal sync lock not
SD horizontal sync lock
Not used
SECAM lock not established
SECAM lock established
Not used
No change in SD signal standard
A change in SD signal standard
No change in SD vertical sync
SD vertical sync lock status has
No change in SD horizontal sync
SD horizontal sync lock status
No change in AD_RESULT[2:0]
AD_RESULT[2:0] bits in Status
No change in SECAM lock status
SECAM lock status has changed
No change in PAL swinging
PAL swinging burst lock status
Not used
established
established
established
Not used
Not used
detected at the input
is detected at the input
lock status
changed
lock status
has changed
bits in Status Register 1
Register 1 have changed
burst lock status
has changed
Not used
These bits
cannot be
cleared or
masked.
Register
0x4A is used
for this
purpose.
These bits
can be
cleared and
masked by
Registers
0x4B and
0x4C,
respectively.
Notes