STA016AP STMicroelectronics, STA016AP Datasheet - Page 15

• Manufacturer Part Number: STA016AP
• Description: DECODER AUDIO MPEG 2.5 64-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA016AP

• Applications: Multimedia
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -

Description :
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
6.2.4
Address : 0xDF (223)
Type : RW - DEC
Software Reset : 3
Description :
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
6.2.5
Address : 0xE0 (224)
Type : RW - DEC
Software Reset : 12
Description :
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
6.2.6
b7
b7
b7
– ofact == 256
– external crystal provide a CRYCK running at
– ofact == 256
– external crystal provide a CRYCK running at
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
14.31818 MHz
14.31818 MHz
PLL_AUDIO_XDIV_192 :
PLL_AUDIO_MDIV_192 :
PLL_AUDIO_PEL_176 :
b6
b6
b6
b5
b5
b5
b4
b4
b4
b3
b3
b3
b2
b2
b2
b1
b1
b1
b0
b0
b0
Address : 0xE1 (225)
Type : RW - DEC
Software Reset : 54
Description :
This register must contain a PEL value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
6.2.7
Address : 0xE2 (226)
Type : RW - DEC
Software Reset : 118
Description :
This register must contain a PEH value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
6.2.8
Address : 0xE3 (227)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
b7
b7
– fact == 256
– external crystal provide a CRYCK running at
– ofact == 256
– external crystal provide a CRYCK running at
– ofact == 256
– external crystal provide a CRYCK running at
14.31818 MHz
14.31818 MHz
14.31818 MHz
PLL_AUDIO_PEH_176 :
PLL_AUDIO_NDIV_176 :
b6
b6
b5
b5
b4
b4
b3
b3
b2
b2
STA016A
b1
b1
15/43
b0
b0