STA016AP STMicroelectronics, STA016AP Datasheet - Page 22

• Manufacturer Part Number: STA016AP
• Description: DECODER AUDIO MPEG 2.5 64-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA016AP

• Applications: Multimedia
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -

STA016A
Table 20. .
6.7.4
Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_4 register description..
6.7.5
Address : 0x5E (94)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate LR clocks (CD_LRCK & BS_LRCK) of CD & BS
input interfaces in audio mode.
22/43
LR15 LR14 LR13 LR12 LR11 LR10
LR7
b7
b7
CF10
CF12
CF13
CF14
CF15
CF11
CF8
CF9
Bit
LR6
b6
b6
I_AUDIO_CONFIG_3 :
I_AUDIO_CONFIG_4 :
Relative synchro :
0 : synchro with first data bit
1 : synchro one bit before first data bit
Data reception configuration :
0 : LSB first
1 : MSB first
Arithmetic type of the reception :
0 : unsigned data
1 : signed data
Bit to select the reference clock used to
generate BCK if clocks are in output
(CF2=1 & CF5=1). Otherwise this bit is
useless.
0 : SYSCK
1 : PCMCK
Reserved : to be set to 1
Reserved : to be set to 1
Reserved : to be set to 0
Reserved : to be set to 0
LR5
b5
b5
LR4
b4
b4
Comment
LR3
b3
b3
LR2
b2
b2
LR9
LR1
b1
b1
LR8
LR0
b0
b0
Table 21.
6.7.6
Address : 0x5F (95)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description.
6.7.7
Address : 0x60 (96)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
6.7.8
Address : 0x61 (97)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16
MA7
MA1
LR[15:12]
Bit fields
b7
b7
b7
LR[11:6]
5
LR[5:0]
MA6
MA1
I_AUDIO_CONFIG_5:
I_AUDIO_CONFIG_7 :
b6
b6
b6
I_AUDIO_CONFIG_6 :
4
Length-1 of phase 1 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
Length-1 of phase 2 of LR clocks
CD_LRCK & BS_LRCK.
Max value is 31.
Reserved : to be set to 0
MA5
MA1
b5
b5
b5
3
MA4
MA1
b4
b4
b4
2
MA3
MA1
Comment
b3
b3
b3
1
MA2
MA1
b2
b2
b2
0
MA1
MA9
b1
b1
b1
MA0
MA8
b0
b0
b0