STA016AP STMicroelectronics, STA016AP Datasheet - Page 21

• Manufacturer Part Number: STA016AP
• Description: DECODER AUDIO MPEG 2.5 64-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA016AP

• Applications: Multimedia
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -

6.7 CDBSA_CONFIGURATION registers
6.7.1
Address : 0x5A (90)
Type : RW - DEC
Software Reset : 0
Description :
If set to 1 enable the configurability of the CD & BS
input interfaces in audio mode thanks to following
registers, else disable this configurability and take
embedded default configuration.
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
6.7.2
Address : 0x5B (91)
Type : RW - DEC
CF7
b7
b7
– I_AUDIO_CONFIG1 = b00010010;
– I_AUDIO_CONFIG2 = b00110010;
– I_AUDIO_CONFIG3 = b11001111;
– I_AUDIO_CONFIG4 = b00000011;
– I_AUDIO_CONFIG5 = 0xFF;
– I_AUDIO_CONFIG6 = 0xFF;
– I_AUDIO_CONFIG7 = 0x00;
– I_AUDIO_CONFIG8 = 0x00;
– I_AUDIO_CONFIG9 = 16;
– I_AUDIO_CONFIG10 = 0x00;
– I_AUDIO_CONFIG11 = 0x00;
description
// clocks in input
// & polarity negative
// synchro with first data bit
// data unsigned, MSB first
// LRCK phase length is 1
// LRCK phase length is 16
// received 16 bits
// received 16 bits
// received 16 bits
// received 16 bits
// data size is 16
// no use because clock in input
// no use because clock in input
CF6
INPUT_CONF :
b6
b6
_AUDIO_CONFIG_1 :
CF5
b5
b5
CF4
b4
b4
CF3
b3
b3
CF2
b2
b2
CF1
b1
b1
CF0
b0
b0
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate CD & BS input interfaces in audio mode
Table 19.
6.7.3
Address : 0x5C (92)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate CD & BS input interfaces in audio mode
CF15 CF14 CF13 CF12 CF11 CF10 CF9
b7
CF0
CF1
CF2
CF3
CF4
CF5
CF6
CF7
Bit
I_AUDIO_CONFIG_2 :
b6
Reserved : to be set to 0
Reserved : to be set to 1
Direction of bit clocks CD_BCK & BS_BCK:
0 : input
1 : output
Polarity of bit clocks CD_BCK & BS_BCK :
0 : data provided on falling edge & stable on
rising edge
1 : data provided on rising edge & stable on
falling edge
Reserved : to be set to 1
Direction of LR clocks CD_LRCK &
BS_LRCK :
0 : input
1 : output
Polarity of LR clocks CD_LRCK &
BS_LRCK :
0 : left sample corresponds to the low level
phase of LRCK
1 : left sample corresponds to the high level
phase of LRCK
Reserved : to be set to 0
b5
b4
Comment
b3
b2
STA016A
b1
CF8
21/43
b0