STA016AP STMicroelectronics, STA016AP Datasheet - Page 20

• Manufacturer Part Number: STA016AP
• Description: DECODER AUDIO MPEG 2.5 64-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA016AP

• Applications: Multimedia
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -

STA016A
6.6.2
Address : 0x5B (91)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register configure the
I2Sin interface
Table 16. .
Table 17.
20/43
CF7
CF[7:5]
b7
fields
CF3
CF0
CF1
CF2
CF3
CF4
Bit
0
1
0
1
CF6
b6
I_AUDIO_CONFIG_1:
Relative synchro :
0 : synchro with first data bit
1 : synchro one bit before first data bit
Data reception configuration :
0 : LSB first
1 : MSB first
Polarity of bit clock BCK :
0 : data provided on falling edge & stable
on rising edge.
1 : data provided on rising edge & stable
on falling edge
Polarity of LR clock LRCK :
0 : negative
1 : positive
Start value of LRCK : combined with CF3,
this bit enable user to determine left/right
couple according to the following table.
Reserved : to be set to 0.
CF4
0
0
1
1
CF5
b5
(data1/data2), (data3/data4),...
(data0/data1), (data2/data3),...
(data0/data1), (data2/data3),...
(data1/data2), (data3/data4),...
CF4
b4
Left/Right couples
Comment
CF3
b3
CF2
b2
CF1
b1
CF0
b0
6.6.3
Address : 0x5C (92)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_3 register description..
6.6.4
Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
ure the phase of the LRCK of the I
Table 18.
0
LR7
Bit fields
LR[15:10] Reserved : to be set to 0
b7
b7
LR[4:0]
LR[9:5]
0
LR6
I_AUDIO_CONFIG_2 :
I_AUDIO_CONFIG_3 :
b6
b6
Position of the data within the LRCK
phase :
- if CF1 = 0 (LSB), value must be set to[31
- SL[9:5] - bit position of the first bit of data
within the LRCK phase].
- if CF1 = 1 (MSB), value must be set to bit
position of the first bit of data within the
LRCK phase.
Note that range of value for this bit
position is [0:31].
Length-1 of the data.
Max value is 31.
0
LR5
b5
b5
0
LR4
b4
b4
Comment
0
LR3
b3
b3
0
LR2
2
b2
b2
Sin.
LR9
LR1
b1
b1
LR8
LR0
b0
b0