HSP43220JC-25Z Intersil, HSP43220JC-25Z Datasheet - Page 10

• Manufacturer Part Number: HSP43220JC-25Z
• Description: IC DECIMATING DGTL FILTER 84PLCC
• Manufacturer: Intersil

Specifications of HSP43220JC-25Z

• Filter Type: Digital
• Number Of Filters: 4
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Cutoff Or Center: -
• Max-order: -

Coefficient RAM
The Coefficient RAM stores the coefficients for the current FIR
filter being implemented. The coefficients are loaded into the
Coefficient RAM over the control bus (C_BUS). The
coefficients are written into the Coefficient RAM sequentially,
starting at location zero. It is only necessary to write one half
of the coefficients when symmetric filters are being
implemented, where the last coefficient to be written in is the
center tap.
The coefficients are loaded into address 01 in two writes.
The first write loads the upper 16 bits of the 20-bit coefficient,
C4 through C19. The second write loads the lower 4 bits of
the coefficient, C0 through C3, where C19 is the MSB. The
two 16-bit writes are then formatted into the 20-bit coefficient
that is then loaded into the Coefficient RAM starting at RAM
address location zero, where the coefficient at this location is
the outer tap (or the first coefficient value).
To reload coefficients, the Coefficient RAM Address pointer
must be reset to location zero so that the coefficients will be
loaded in the order the FIR filter expects. There are two
methods that can be used to reset the Coefficient RAM
address pointer. The first is to assert RESET, which
automatically resets the pointer, but also clears the HDF and
alters some of the control register bits. (RESET does not
change any of the coefficient values.) The second method is
to set the F_DIS bit in control register H_ REGISTER1. This
control bit allows any of the FIR control register bits to be re-
programmed, but does not automatically modify any control
registers. When the programming is completed, the FIR is
re-started by clearing the F_DIS bit or by asserting one of
the start inputs (ASTARTIN or STARTIN). The F_DIS bit
allows the filter parameters to be changed more quickly and
is thus the recommended reprogramming method.
Data RAM
The Data RAM stores the data needed for the filter
calculation. The format of the data is:
2
where the sign bit is in the 2
The 16-bit output of the HDF Output Register is written into
the Data Ram on the rising edge of CK_DEC.
RESET initializes the write pointer to the data RAM. After a
RESET occurs, the output of the FIR will not be valid until
the number of new data samples written to the Data RAM
equals TAPS.
The filter always operates on the most current sample and
the taps-1 previous samples. Thus if the F_DIS bit is set,
data continues to be written into the data RAM coming from
the HDF section. When the FIR is enabled again the filter will
be operating on the most current data samples and thus
another transient response will not occur.
0
.2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
0
10
-9
location.
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
HSP43220
The maximum throughput of the FIR filter is limited by the
use of a single Multiplier/Accumulator (MAC). The data
output from the HDF being clocked into the FIR filter by
CK_DEC must not be at a rate that causes an erroneous
result being calculated because data is being overwritten.
Equation 2 describes the relationship between, FIR_CK,
CK_DEC, the number of taps that can be implemented in the
FIR, the decimation rate in the HDF and the decimation rate
in the FIR. (In the Design Considerations section of the
“Operational Section” on page 12 there is a chart that shows
the tradeoffs between these parameters.)
This equation expresses the minimum FIR_CK. The
minimum FIR_CK is the smallest integer multiple of CK_IN
that satisfies Equation 1. In addition, the TSK specification
must be met (see AC Electrical Specifications). F
decimation rate in the FIR (F
TAPS = the number of taps in the FIR for even length filters
and equals the number of taps+1 for odd length filters.
Solving Equation 3 for the maximum number of taps:
In using this equation, it must be kept in mind that CK_IN/
H
is in bypass mode in which case this limitation in the HDF
does not apply). In the “Operational Section” on page 12
under the Design Considerations, there is a table that shows
the trade-offs of these parameters. In addition, Intersil
provides a software package called DECI MATE™ which
designs the DDF filter from System specifications.
The registered outputs of the data RAM are added or
subtracted in the 17-bit pre-adder. The F_OAD control bit
allows zeros to be input into one side of the pre-adder. This
provides the capability to implement non-symmetric filters.
The selection of adding the register outputs for an even
symmetric filter or for subtracting the register outputs for odd
symmetric filter is provided by the control bit F_ESYM, which
is programmed over the control bus. When subtraction is
selected, the new data is subtracted from the old data. The
17-bit output of the adder forms one input of the
multiplier/accumulator.
A control bit F_CLA provides the capability to clear the
feedback path in the accumulator such that multiplier output will
not be accumulated, but will instead flow directly to the output
register. The bit weightings of the data and coefficients as they
are processed in the FIR is shown as follows.
Input Data (from HDF) 2
Pre-adder Output 2
Coefficient 2
Accumulator 2
FIR_CK
TAPS
DEC
must be less than or equal to 4MHz (unless the HDF
=
≥
2
CK_IN TAPS/2
--------------------------------------------------------------------------------- -
⎛
⎝
FIR_CK H
--------------------------------------------------------- - F
0
.2
8
[
(
-1
. . . 2
H
CK_IN
DEC
. . . 2
1
DEC
2
0
0
F
.2
-19
.2
)
DEC
0
F
-1
1
+
.2
DEC
. . . 2
4
DEC
-1
. . . 2
+
. . . 2
F
–
DEC
-34
= F_DRATE +1), where
-15
DEC
-15
]
-4
⎞
⎠
October 10, 2008
DEC
FN2486.10
is the
(EQ. 2)
(EQ. 3)