HSP43220JC-25Z Intersil, HSP43220JC-25Z Datasheet - Page 8

• Manufacturer Part Number: HSP43220JC-25Z
• Description: IC DECIMATING DGTL FILTER 84PLCC
• Manufacturer: Intersil

Specifications of HSP43220JC-25Z

• Filter Type: Digital
• Number Of Filters: 4
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Cutoff Or Center: -
• Max-order: -

DDF Control Registers
H_Register 1 (A1 = 1, A0 = 0)
15
RESERVED
14
13
F_DIS
FD0
12
F_CLA
FC0
11
8
(Continued)
H_BYP
HB0
10
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
9
H_DRATE Bits
R0-R9 are used to select the amount of decimation in the HDF. The amount of
decimation selected is programmed as the required decimation minus one; for
instance to select decimation of 1024 H_DRATE is set equal to 1023. HDRATE +1 is
defined as H
H_BYP
Bit HB0 is used to select HDF bypass mode. This mode is selected by setting
H_BYP = 1. When this mode is selected the input data passes through the HDF
unfiltered. Internally H_STAGES and H_DRATE are both set to zero and H_GROWTH
is set to 50. H_REGISTER 2 must be reloaded when H_BYP is returned to 0. To disable
HDF bypass mode H_BYP = 0. The relationship between CK_IN and FIR_CK in this
and all other modes is defined by Equation 2.
F_CLA
Bit FC0 is used to select the clear accumulator mode in the FIR. This mode is enabled
by setting F_CLA = 1 and is disabled by setting F_CLA = 0. In normal operation this bit
should be set equal to zero. This mode zeros the feedback path in the accumulator of
the multiplier/accumulator (MAC). It also allows the multiplier output to be clocked off
the chip by FIR_CK, thus DATA_RDY has no meaning in this mode. This mode can be
used in conjunction with the F_OAD bit to read out the FIR coefficients from the
coefficient RAM.
F_DIS
Bit FD0 is used to select the FIR disable mode. This feature enables the FIR parameters
to be changed. This feature is selected by setting F_DIS = 1. This mode terminates the
current FIR cycle. While this feature is selected, the HDF continues to process data and
write it into the FIR data RAM. When the FIR re-programming is completed, the FIR can
be re-enabled either by clearing F_DIS, or by asserting one of the start inputs, which
automatically clears F_DIS.
8
7
HSP43220
DEC
6
FIGURE 6.
H_DRATE
.
5
4
3
2
1
0
October 10, 2008
FN2486.10