HSP43220JC-25Z Intersil, HSP43220JC-25Z Datasheet - Page 2

• Manufacturer Part Number: HSP43220JC-25Z
• Description: IC DECIMATING DGTL FILTER 84PLCC
• Manufacturer: Intersil

Specifications of HSP43220JC-25Z

• Filter Type: Digital
• Number Of Filters: 4
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Cutoff Or Center: -
• Max-order: -

Block Diagram
Pinout
Pin Description
FIR_CK
NAME
CK_IN
GND
V
CC
TYPE
I
I
CONTROL AND COEFFICIENTS
The +5V power supply pins.
The device ground.
Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock
frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN
can be divided down from FIR_CK. CK_IN is a CMOS level signal.
Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the
rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal.
STARTOUT
ASTARTIN
C_BUS 15
C_BUS 14
C_BUS 13
C_BUS 12
C_BUS 11
C_BUS 10
STARTIN
C_BUS 9
C_BUS 8
C_BUS 7
C_BUS 6
RESET
2
GND
V
V
WR
CS
CC
A1
A0
CC
INPUT CLOCK
DATA INPUT
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
84 PLASTIC LEADED CHIP CARRIER (PLCC)
16
16
DECIMATION UP TO 1024
HIGH ORDER
DECIMATION
HSP43220
FILTER
HSP43220
TOP VIEW
DESCRIPTION
DECIMATION UP TO 16
DECIMATION
FIR CLOCK
FILTER
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
FIR
GND
DATA_OUT 0
DATA_OUT 1
DATA_OUT 2
DATA_OUT 3
DATA_OUT 4
DATA_OUT 5
DATA_OUT 6
DATA_OUT 7
DATA_OUT 8
DATA_OUT 9
DATA_OUT 10
DATA_OUT 11
GND
V
DATA_OUT 12
DATA_OUT 13
DATA_OUT 14
DATA_OUT 15
DATA_OUT 16
DATA_OUT 17
CC
24
DATA OUT
DATA READY
October 10, 2008
FN2486.10