MCP23016-I/SP Microchip Technology, MCP23016-I/SP Datasheet - Page 24

• Manufacturer Part Number: MCP23016-I/SP
• Description: IC I/O EXPANDER I2C 16B 28SDIP
• Manufacturer: Microchip Technology

Specifications of MCP23016-I/SP

• Package / Case: 28-DIP (0.300", 7.62mm)
• Interface: I²C
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Includes: POR
• Logic Family: MCP23016
• Propagation Delay Time: 50 ns
• Operating Supply Voltage: 2 V to 5.5 V
• Power Dissipation: 1 W
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 4.5 V to 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 400 KHz
• Maximum Operating Frequency: 3.4 MHz
• Mounting Style: Through Hole
• Output Current: 25 mA
• Output Voltage: 4.5 V
• Chip Configuration: 16 Bit
• Bus Frequency: 400kHz
• Ic Interface Type: I2C
• No. Of I/o's: 16
• Supply Voltage Range: 2V To 5.5V
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Ic Function: I/O Expander
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MCP23016
TABLE 2-5:
DS20090C-page 24
Note 1:
Param
No.
100
101
102
103
106
107
109
110
111
90
91
92
2:
3:
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A Fast mode (400 kHz) I
requirement T
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line T
Standard mode I
Symbol
T
T
T
T
T
T
SU
SU
T
T
SU
HD
HD
T
T
HIGH
WAIT
C
LOW
T
T
BUF
AA
:
:
:
:
:
R
F
B
STA
DAT
STO
DAT
STA
I
2
C BUS DATA REQUIREMENTS
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
START Condition
Setup Time
START Condition
Hold Time
Data Input Hold
Time
Data Input Setup
Time
STOP Condition
Setup Time
Output Valid from
Clock
Bus Free Time
Bus Capacitive Loading
Clock wait time
after ninth pulse
SU
:
2
DAT
C bus specification), before the SCL line is released.
≥ 250 ns must then be met. This will automatically be the case if the device does not
Characteristic
2
C bus device can be used in a Standard mode (100 kHz) I
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode 20 + 0.1 C
100 kHz mode
400 kHz mode 20 + 0.1 C
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
R
max.+T
12 µs
12 µs
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
SU
:
DAT
B
B
1000
3500
Max
= 1000 + 250 = 1250 ns (according to the
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
pF
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
µs
µs
© 2007 Microchip Technology Inc.
(Note 1)
(Note 1)
(Note 1)
C
10 - 400 pF
(Note 1)
C
10 - 400 pF
Only relevant for repeated
START condition (Note 1)
After this period, the first
clock pulse is generated
(Note 1)
(Note 1)
(Note 1) (Note 3)
(Note 1)
(Note 1) (Note 2)
Time the bus must be free
before a new transmis-
sion can start (Note 1)
Time the bus must remain
free after the ninth clock
pulse before a new
transmission can start.
B
B
2
is specified to be from
is specified to be from
C bus system, but the
Conditions