AD9824KCP Analog Devices Inc, AD9824KCP Datasheet
AD9824KCP
Specifications of AD9824KCP
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AD9824KCP Summary of contents
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FEATURES 14-Bit 30 MSPS A/D Converter 30 MSPS Correlated Double Sampler (CDS 6-Bit Pixel Gain Amplifier ( PxGA 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function ...
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AD9824–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Standby Total Power-Down MAXIMUM CLOCK RATE A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage Data ...
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CCD-MODE SPECIFICATIONS Parameter P OWER CONSUMPTION MAXIMUM CLOCK RATE CDS Gain 1 Allowable CCD Reset Transient 1 Max Input Range Before Saturation 1 Max CCD Black Pixel Amplitude PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control ...
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AD9824–SPECIFICATIONS AUX1-MODE SPECIFICATIONS Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER Gain Max Input Range VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS ...
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... INH 7 SCLK Model Unit AD9824KCP V V THERMAL CHARACTERISTICS V Thermal Resistance 48-Lead LFCSP Package V θ = 26°C/ θ is measured using a 4-layer PCB with the exposed paddle V JA soldered to the board °C 150 °C 300 –5– AD9824 Typ Max Unit 33 ns 16 ...
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AD9824 CONNECT Pin Number Name 1–12 D2–D13 13 DRVDD 14 DRVSS 15, 41 DVSS 16 DATACLK 17 DVDD1 PBLK 20 CLPOB 21 SHP 22 SHD 23 CLPDM 24 VD 25, 26, 35 AVSS 27 ...
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DEFINITIONS OF SPECIFICATIONS Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 14-bit ...
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AD9824 –Typical Performance Characteristics 190 180 170 V = 3.3V DD 160 150 V = 3.0V DD 140 130 V = 2.7V DD 120 110 100 10 20 SAMPLE RATE – MHz TPC 1. Power vs. Sample Rate 0.5 0.25 ...
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CCD MODE AND AUX MODE TIMING CCD SIGNAL SHP t S1 SHD t INH DATACLK t OD OUTPUT N–10 DATA NOTES 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND ...
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AD9824 PIXEL GAIN AMPLIFIER (PxGA) TIMING FRAME N VD 0101... 2323... 0101... LINE 0 LINE 1 LINE GAIN0 GAIN1 GAIN2 GAIN3 Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain ...
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LINE N VD 012012012... GAIN0 GAIN1 GAIN2 Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence 5 PIXEL MIN VD 5 PIXEL MIN HD SHP PxGA GAIN NOTES 1. BOTH VD AND ...
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AD9824 VD EVEN FIELD 0101... 0101... 0101... LINE 0 LINE 1 LINE GAIN0 GAIN1 GAIN2 GAIN3 Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence VD 5 PIXEL ...
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VD HD 3ns MIN SHP PxGA GAIN GAIN0 NOTES 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES AND SELECTS GAIN0 AND SELECTS ...
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AD9824 SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Register Address Name Operation Channel Select Power-Down CCD/AUX1/2 Modes VGA Gain LSB Clamp Level LSB Control 1 ...
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BITS RNW A0 A1 OPERATION A2 ... SDATA ... SCK NOTES 1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS ...
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AD9824 Table IV. Clamp Level Register Contents (Default Value x080) MSB D10 Table V. Control Register Contents (Default Value x000) Data Out DATACLK ...
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CIRCUIT DESCRIPTION AND OPERATION The AD9824 signal processing chain is shown in Figure 25. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. DC Restore To reduce the large dc offset of ...
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AD9824 MOSAIC SEPARATE COLOR CCD: PROGRESSIVE BAYER STEERING MODE Gr LINE0 GAIN0, GAIN1, GAIN0, GAIN1... LINE1 GAIN2, GAIN3, GAIN2, GAIN3... LINE2 GAIN0, GAIN1, GAIN0, GAIN1... ...
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A/D Converter The AD9824 uses high performance ADC architecture, opti- mized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB, as shown in TPC 2. Instead of the 1 V full-scale range used ...
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AD9824 APPLICATIONS INFORMATION The AD9824 is a complete analog front end (AFE) product for digital still camera and camcorder applications. As shown in Figure 32, the CCD image (pixel) data is buffered and sent to the AD9824 analog input through ...
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SERIAL INTERFACE (MSB) D13 14 DATA OUTPUTS 3V DRIVER SUPPLY Figure 33. Recommended Circuit Configuration for CCD-Mode Internal Power-On Reset Circuitry After power-on, the AD9824 will automatically reset all internal registers and perform internal calibration procedures. This takes approximately 1 ...
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AD9824 12 MAX 0.90 (0.0354) MAX 0.85 (0.0335) NOM 0.20 (0.0079) REF SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches) 48-Lead Frame Chip Scale Package LFCSP Body (CP-48) 0.60 (0.0236) 0.42 (0.0165) 7.00 (0.2756) ...
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