AD9824KCP Analog Devices Inc, AD9824KCP Datasheet - Page 12

• Manufacturer Part Number: AD9824KCP
• Description: IC CCD SIGNAL PROC 14BIT 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9824KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 14b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9824
HD
VD
HD
PxGA GAIN
VD
PxGA GAIN
*0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
* 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
SHP
SHP
VD
HD
VD
HD
0101...
LINE 0
0101...
LINE 0
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323... (ODD).
NOTES
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SETUP TIME IS 3 ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
3ns MIN
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
0101...
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
LINE 1
1212...
LINE 1
EVEN FIELD
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
5 PIXEL MIN
FRAME N
5 PIXEL MIN
0101...
LINE 2
0101...
LINE 2
LINE M–1
LINE M–1
3ns MIN
GAINX
LINE M
LINE M
–12–
3ns MIN
GAINX
GAIN0
2323...
LINE 0
0101...
3ns MIN
LINE 0
GAIN1
GAIN0
GAIN0
GAIN1
2323...
LINE 1
1212...
LINE 1
ODD FIELD
GAINX
FRAME N+1
GAIN0
2323...
LINE 2
0101...
LINE 2
GAIN2
GAINX
LINE M–1
LINE M–1
GAIN3
GAIN1
GAIN2
LINE M
LINE M
REV. 0