AD9824KCP Analog Devices Inc, AD9824KCP Datasheet - Page 18

• Manufacturer Part Number: AD9824KCP
• Description: IC CCD SIGNAL PROC 14BIT 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9824KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 14b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9824
The same Bayer pattern can also be interlaced, and the VD
selected mode should be used with this type of CCD (see
Figure 27). The color steering performs the proper multiplexing
of the R, G, and B gain values (loaded into the PxGA gain regis-
ters) and is synchronized by the user with vertical (VD) and
horizontal (HD) sync pulses. For more detailed information, see
the PxGA Timing section. The PxGA gain for each of the four
channels is variable from –2.5 dB to +9.5 dB, controlled in 64
steps through the serial interface. The PxGA gain curve is
shown in Figure 28.
Figure 26. CCD Color Filter Example: Progressive Scan
Figure 27. CCD Color Filter Example: Interlaced
CCD: PROGRESSIVE BAYER
CCD: INTERLACED BAYER
(100000)
Gb
Gb
Gb
Gb
10
–2
–4
R
R
R
R
Gb
Gb
8
6
4
2
0
R
R
32
ODD FIELD
EVEN FIELD
Gr
Gr
Gr
Gr
B
B
B
B
Gr
Gr
B
B
40
Gb
Gb
Gb
Gb
Figure 28. PxGA Gain Curve
R
R
R
R
Gb
Gb
R
R
Gr
Gr
Gr
Gr
48
B
B
B
B
Gr
Gr
B
B
PxGA GAIN REGISTER CODE
LINE0
LINE1
LINE2
LINE0
LINE1
LINE2
LINE0
LINE1
LINE2
58
MOSAIC SEPARATE COLOR
STEERING MODE
VD SELECTED COLOR
STEERING MODE
0
GAIN0, GAIN1, GAIN0, GAIN1...
GAIN0, GAIN1, GAIN0, GAIN1...
GAIN0, GAIN1, GAIN0, GAIN1...
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN0, GAIN1, GAIN0, GAIN1...
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN0, GAIN1, GAIN0, GAIN1...
8
16
24
(011111)
31
–18–
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with approximately 4 dB from the PxGA stage, the
total gain range for the AD9824 is 6 dB to 40 dB. The minimum
gain of 6 dB is needed to match -a 1 V input signal with the
ADC full-scale range of 2 V. When compared to 1 V full-scale
systems (such as ADI’s AD9803), the equivalent gain range is
0 dB to 34 dB.
The VGA gain curve follows a “linear-in-dB” shape. The exact
VGA gain can be calculated for any gain register value by using
the following equation:
Code Range Gain Equation (dB)
0–1023
As shown in the CCD Mode Specifications, only the VGA gain
range from 2 dB to 36 dB has tested and guaranteed accuracy.
This corresponds to a VGA gain code range of 77 to 1023. The
Gain Accuracy Specifications also include a PxGA gain of approxi-
mately 3.3 dB, for a total gain range of 6 dB to 40 dB.
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the clamp level
register. The clamp level is adjustable from 0 to 1020 LSB, in
256 steps. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the post processing, the AD9824 optical black
clamping may be disabled using Bit D5 in the Operation Register
(see Serial Interface Timing and Internal Register Description
section). When the loop is disabled, the clamp level register may
still be used to provide programmable offset adjustment.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase and the ability to track
low frequency variations in the black level will be reduced.
Figure 29. VGA Gain Curve (Gain from PxGA Not Included)
36
30
24
18
12
6
0
0
127
Gain = (0.0353)(Code)
255
VGA GAIN REGISTER CODE
383
511
639
767
895
1023
REV. 0