AD9824KCP Analog Devices Inc, AD9824KCP Datasheet - Page 17

• Manufacturer Part Number: AD9824KCP
• Description: IC CCD SIGNAL PROC 14BIT 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9824KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 14b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

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CIRCUIT DESCRIPTION AND OPERATION
The AD9824 signal processing chain is shown in Figure 25.
Each processing step is essential in achieving a high quality image
from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5 V to be compatible with the 3 V single supply of
the AD9824.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 5 illustrates how the two CDS clocks, SHP
and SHD, are used to sample the reference level and data level
of the CCD signal, respectively. The CCD signal is sampled on
the rising edges of SHP and SHD. Placement of these two clock
signals is critical in achieving the best performance from the CCD.
An internal SHP/SHD delay (t
propagation delays.
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded black
reference pixels. Unlike some AFE architectures, the AD9824
removes this offset in the input stage to minimize the effect of a
0.1 F
CLPDM
CCDIN
VD
HD
ID
) of 3 ns is caused by internal
INPUT OFFSET
CLAMP
DC RESTORE
CDS
–2dB TO +10dB
Figure 25. CCD Mode Block Diagram
PxGA
6
STEERING
COLOR
2
MUX
4:1
REGISTER
VGA GAIN
VGA
2dB TO 36dB
GAIN0
GAIN1
GAIN2
GAIN3
–17–
10
3
gain change on the system black level. Another advantage of
removing this offset at the input stage is to maximize system
headroom. Some area CCDs have large black level offset volt-
ages, which, if not corrected at the input stage, can significantly
reduce the available headroom in the internal circuitry when
higher VGA gain settings are used.
Horizontal timing is shown in Figure 6. It is recommended
that the CLPDM pulse be used during valid CCD dark pixels.
CLPDM may be used during the optical black pixels, either
together with CLPOB or separately. The CLPDM pulse should
be a minimum of 4 pixels wide.
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA has the capability to “multiplex” its gain value
on a pixel-to-pixel basis. This allows lower output color pixels to
be gained up to match higher output color pixels. Also, the PxGA
may be used to adjust the colors for white balance, reducing the
amount of digital processing that is needed. The four different gain
values are switched according to the color steering circuitry.
Seven different color steering modes for different types of CCD
color filter arrays are programmed in the AD9824’s Control Regis-
ter. For example, mosaic separate steering mode accommodates
the popular “Bayer” arrangement of red, green, and blue filters
(see Figure 26).
PxGA MODE
SELECTION
REGISTERS
PxGA GAIN
8-BIT
DAC
FILTERING
DIGITAL
OPTICAL BLACK
INTERNAL
CLAMP
14-BIT
V
ADC
REF
2V FULL SCALE
CLAMP LEVEL
REGISTER
8
14
CLPOB
DOUT
AD9824