AD9948KCP Analog Devices Inc, AD9948KCP Datasheet
AD9948KCP
Specifications of AD9948KCP
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AD9948KCP Summary of contents
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FEATURES Correlated Double Sampler (CDS Pixel Gain Amplifier ( PxGA 10-Bit Variable Gain Amplifier (VGA) 10-Bit 25 MSPS A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing ...
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AD9948–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) HVDD (H1–H4 Drivers) RGVDD (RG Driver) DRVDD (D0–D9 Drivers) DVDD (All Other Digital) POWER DISSIPATION 25 MHz, HVDD = RGVDD = ...
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ANALOG SPECIFICATIONS Parameter CDS Gain Allowable CCD Reset Transient* Max Input Range before Saturation* Max CCD Black Pixel Amplitude* PIXEL GAIN AMPLIFIER (PxGA) Gain Control Resolution Gain Monotonicity Min Gain Max Gain VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max ...
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... AD9948KCPRL –20°C to +85°C AD9948KCPZ* –20°C to +85°C AD9948KCPZRL* –20°C to +85°C *This is a lead free product. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9948 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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Pin No. Mnemonic 2–4 D0–D2 5 DRVSS 6 DRVDD 7–13 D3– HVSS 17 HVDD RGVSS RGVDD 23 TCVSS 24 TCVDD 25 CLI 26 AVDD 27 CCDIN 28 ...
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AD9948 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit resolution ...
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ADC OUTPUT CODE TPC 1. Typical DNL 10 7.5 5.0 2 400 200 600 VGA GAIN CODE (LSB) TPC 2. Output Noise vs. VGA Gain 275 250 225 V ...
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AD9948 SYSTEM OVERVIEW V-DRIVER V1–Vx, VSG1–VSGx, SUBCK H1–H4, RG CCDIN AD9948 CCD INTEGRATED AFE + TD SERIAL INTERFACE Figure 1. Typical Application Figure 1 shows the typical system application diagram for the AD9948. The CCD output is processed by the ...
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SERIAL INTERFACE TIMING All of the internal registers of the AD9948 are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit data- word are written starting ...
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AD9948 Data Bit Default Address Content Value Name 00 [11:0] 4 OPRMODE 01 [9:0] 0 VGAGAIN 02 [7:0] 80 CLAMP LEVEL 03 [11:0] 4 CTLMODE 04 [17:0] 0 PxGA GAIN01 05 [17:0] 0 PxGA GAIN23 Data Bit Default Address Content ...
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Data Bit Default Address Content Value (Hex) 20 [3: [23:0] FFFFFF 22 [23:0] FFFFFF 23 [23:0] FFFFFF 24 [23:0] FFFFFF 0 25 [7: [11:0] FFF 27 [11:0] FFF 28 [11:0] FFF Data Bit Default Address Content ...
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AD9948 Data Bit Default Address Content Value (Hex [3: [23:0] FFFFFF 45 [23:0] FFFFFF 46 [23:0] FFFFFF 47 [23:0] FFFFFF 48 [23:0] FFFFFF 49 [23:0] FFFFFF 4A [23:0] ...
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Data Bit Default Address Content Value Name 00 [1:0] 0 PWRDOWN [2] 1 CLPENABLE [3] 0 CLPSPEED [4] 0 FASTUPDATE [5] 0 PBLK_LVL [7:6] 0 TEST MODE [8] 0 DCBYP [9] 0 TESTMODE [11:10] 0 CDSGAIN Data Bit Default Address ...
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AD9948 PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9948 generates flexible high speed timing signals using the Precision Timing core. This core is the foundation for gener- ating the timing used for both the CCD and the AFE; the reset ...
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Quadrant Edge Location (Decimal III H-Driver and RG Outputs In addition to the programmable timing positions, the AD9948 features on-chip output drivers for the RG ...
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AD9948 HORIZONTAL CLAMPING AND BLANKING The AD9948’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual sequences are defined for each signal, which are then organized into multiple regions during image readout. This allows ...
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HD HBLK H1/H3 H1/H3 H2/H4 TOG1 HBLK H1/H3 H2/H4 SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS. Table XIV. Horizontal Sequence Control Parameters for CLPOB, PBLK, and HBLK Register Length SCP 12b SPTR 2b GENERATING SPECIAL HBLK PATTERNS ...
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AD9948 SEQUENCE CHANGE OF POSITION 0 SEQUENCE CHANGE OF POSITION 1 SEQUENCE CHANGE OF POSITION 2 SEQUENCE CHANGE OF POSITION FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE ...
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POWER-UP PROCEDURE VDD (INPUT) CLI (INPUT) t PWR SERIAL WRITES VD (OUTPUT) HD (OUTPUT) H2/H4 DIGITAL H1/H3, RG OUTPUTS Recommended Power-Up Sequence When the AD9948 is powered up, the following sequence is recommended (refer to Figure 14 for each step): ...
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AD9948 DC RESTORE 1.5V SHP SHD 1.0 F CCDIN CDS 0dB, –2dB, –4dB SHP SHD PRECISION TIMING GENERATION Figure 15. Analog Front End Functional Block Diagram ANALOG FRONT END DESCRIPTION AND OPERATION The AD9948 signal processing chain is shown in ...
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CCD: PROGRESSIVE BAYER COLOR STEERING MODE: PROGRESSIVE LINE0 GAIN0, GAIN1, GAIN0, GAIN1, ... LINE1 GAIN2, GAIN3, GAIN2, GAIN3, ... LINE2 GAIN0, GAIN1, GAIN0, GAIN1, ... ...
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AD9948 FIELDVAL = 0 FIELDVAL VD HD PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE FALLING EDGES WILL ALTERNATE THE PxGA GAIN ...
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The PxGA gain for each of the four channels is variable from 512 steps, specified using the PxGA GAIN01 and PxGA GAIN23 registers. The PxGA gain curve is shown in Figure 19. The PxGA ...
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AD9948 APPLICATIONS INFORMATION Circuit Configuration The AD9948 recommended circuit configuration is shown in Figure 21. Achieving good image quality from the AD9948 requires careful attention to PCB layout. All signals should be routed to maintain low noise performance. The CCD ...
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Driving the CLI Input The AD9948’s master clock input (CLI) may be used in two different configurations, depending on the application. Figure 23a shows a typical dc-coupled input from the master clock source. When the dc-coupled technique is used, the ...
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AD9948 HORIZONTAL TIMING SEQUENCE EXAMPLE Figure 24 shows an example CCD layout. The horizontal regis- ter contains 28 dummy pixels, which will occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) ...
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SEQUENCE 2: VERTICAL OPTICAL BLACK LINES CCDIN VERTICAL SHIFT OPTICAL BLACK SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB Figure 26. Horizontal Sequences during Vertical Optical Black Pixels SEQUENCE 3: EFFECTIVE PIXEL LINES VERTICAL SHIFT CCDIN OPTICAL BLACK SHP SHD H1/H3 ...
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AD9948 PIN 1 INDICATOR 12 MAX 1.00 0.90 0.80 SEATING PLANE OUTLINE DIMENSIONS 40-Lead Lead Frame Chip Scale Package [LFCSP Body (CP-40) Dimensions shown in millimeters 6.00 BSC SQ 0.60 MAX 0.50 BSC TOP 5.75 VIEW ...