DS90UR241IVS/NOPB National Semiconductor, DS90UR241IVS/NOPB Datasheet - Page 16

• Manufacturer Part Number: DS90UR241IVS/NOPB
• Description: IC SER/DESER 5-43MHZ 24B 48-TQFP
• Manufacturer: National Semiconductor

Specifications of DS90UR241IVS/NOPB

• Function: Serializer/Deserializer
• Data Rate: 1.03Gbps
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 1
• Number Of Outputs: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• For Use With: SERDESUR-43USB - BOARD EVAL DS90UR124,DS90UR241
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS90UR241IVS/NOPB; DS90UR241IVSCT; DS90UR241IVSCT

www.national.com
49
63
64
23
50
1-6,
17, 18,
33, 34
BIST MODE PINS(See Applications Informations section for more details.)
61
62
45
LVDS SERIAL INTERFACE PINS
53
54
POWER / GROUND PINS
51
52
59
58
57
56
32
31
46
47
40
39
26
25
11
12
Pin #
PTOSEL
RAOFF
SLEW
LOCK
RES0
RES0
BISTEN
BISTM
PASS
R
R
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
IN+
IN−
Pin Name
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_O
LVCMOS_I
NC
LVCMOS_I
LVCMOS_I
LVCMOS_O
LVDS_I
LVDS_I
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
I/O/PWR
Progressive Turn On Operation Selection
PTO = H; R
±1 UI to ±2 UI apart relative to RCLK.
PTO = L; PTO Spread Mode, R
±1 UI.
Randomizer Control Input Pin (See Table 2 for more details.)
RAOFF = H, Backwards compatible mode for use with DS90C241 Serializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
LVCMOS Output Slew Rate Control
SLEW = L; Low drive output at 2 mA (default)
SLEW = H; High drive output at 4 mA
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, R
Reserved. This pin MUST be tied LOW.
No Connection. Pins are not physically connected to the die. Recommendation is to leave pin
open or tie it to LOW.
Control Pin for BIST Mode Enable
BISTEN = L; Default at Low, Normal Mode.
BISTEN = H; BIST mode active. When BISTEN = H and DS90UR241 DIN[23:0] = Low or
Floating; device will go to BIST mode accordingly. Check PASS output pin for test status.
BIST Mode selection. Control pin for which Deserializer is set for BIST reporting mode.
BISTM = L; Default at Low, Status of all R
BISTM = H; Total accumulated bit error count provided on ROUT[7:0] (binary counter up to 255)
Pass flag output for @Speed BIST Test operation.
PASS = L; BIST failure
PASS = H; LOCK = H before BIST can be enabled, then 1x10
Receiver LVDS True (+) Input — This input is intended to be terminated with a 100Ω load to
the R
Receiver LVDS Inverted (−) Input — This input is intended to be terminated with a 100Ω load
to the R
Analog LVDS Voltage Supply, POWER
Analog LVDS GROUND
Analog Voltage Supply, PLL POWER
Analog Ground, PLL GROUND
Analog Voltage supply, PLL VCO POWER
Analog Ground, PLL VCO GROUND
Digital Voltage Supply, LOGIC POWER
Digital Ground, Logic GROUND
Digital Voltage Supply, LOGIC POWER
Digital Ground, LOGIC GROUND
Digital Voltage Supply, LVCMOS Output POWER
Digital Ground, LVCMOS Output GROUND
Digital Voltage Supply, LVCMOS Output POWER
Digital Ground, LVCMOS Output GROUND
Digital Voltage Supply, LVCMOS Output POWER
Digital Ground, LVCMOS Output GROUND
IN+
(Figure
IN-
pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
OUT
16) See Applications Informations section for more details.
[23:0] are grouped into three groups of eight, with each group switching about
16
OUT
[23:0] outputs are spread ±1 UI to ±2 UI and RCLK spread
(Figure
OUT
Description
OUT
[23-0] and RCLK are at TRI-STATE.
with respective bit error on cycle-by-cycle basis
15)
-9
error rate achieved across link.