DS90UR241IVS/NOPB National Semiconductor, DS90UR241IVS/NOPB Datasheet - Page 19

• Manufacturer Part Number: DS90UR241IVS/NOPB
• Description: IC SER/DESER 5-43MHZ 24B 48-TQFP
• Manufacturer: National Semiconductor

Specifications of DS90UR241IVS/NOPB

• Function: Serializer/Deserializer
• Data Rate: 1.03Gbps
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 1
• Number Of Outputs: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• For Use With: SERDESUR-43USB - BOARD EVAL DS90UR124,DS90UR241
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS90UR241IVS/NOPB; DS90UR241IVSCT; DS90UR241IVSCT

for the pullup and pulldown. Ratio the resistor values to bias
the center point at 1.8V. For example (see
V
Rpullup=100Ω, Rpulldown= 120Ω (strongest). The smaller
values will consume more bias current, but will provide en-
hanced noise suppression.
SIGNAL QUALITY ENHANCERS
The DS90UR124 Deserializer supports two signal quality en-
hancers. The SLEW pin is used to increase the drive strength
of the LVCMOS outputs when driving heavy loads. SLEW al-
lows output drive strength for high or low current drive. Default
setting is LOW for low drive at 2 mA and HIGH for high drive
at 4 mA.
There are two types of Progressive Turn-On modes (Fixed
and PTO Frequency Spread) to help reduce EMI, simultane-
ous switching noise, and system ground bounce. The
PTOSEL pin introduces bank skew in the data/clock outputs
to limit the number of outputs switching simultaneously. For
Fixed-PTO mode, the Deserializer ROUT[23:0] outputs are
grouped into three groups of eight, with each group switching
about 2 or 1 UI apart in phase from RCLK for Group 1 and
Groups 2, 3 respectively (see
quency Spread mode, ROUT[23:0] are also grouped into
three groups of eight, with each group is separated out of
phase with the adjacent groups (see
cycles. Note that in the PTO Frequency Spread operating
mode RCLK is also spreading and separated by 1 UI.
@SPEED-BIST TEST FEATURE
To assist vendors with test verification, the DS90UR241/
DS90UR124 is equipped with built-in self-test (BIST) capa-
bility to support both system manufacturing and field diag-
nostics. BIST mode is intended to check the entire high-speed
serial link at full link-speed, without the use of specialized and
expensive test equipment. This feature provides a simple
method for a system host to perform diagnostic testing of both
Serializer and Deserializer. The BIST function is easily con-
figured through the 2 control pins on the DS90UR124. When
the BIST mode is activated, the Serializer has the ability to
transfer an internally generated PRBS data pattern. This pat-
tern traverses across interconnecting links to the Deserializer.
The DS90UR124 includes an on-chip PRBS pattern verifica-
tion circuit that checks the data pattern for bit errors and
reports any errors on the data output pins on the Deserializer.
The @SPEED-BIST feature uses 2 signal pins (BISTEN and
BISTM) on the DS90UR124 Deserializer. The BISTEN and
BISTM pins together determine the functions of the BIST
mode. The BISTEN signal (HIGH) activates the test feature
on the Deserializer. After the BIST mode is enabled, all the
data input channels DIN[23:0] on the DS90UR241 Serializer
must be set logic LOW or floating in order for Deserializer to
start accepting data. An input clock signal (TCLK) for the Se-
rializer must also be applied during the entire BIST operation.
The BISTM pin selects error reporting status mode of the
BIST function. When BIST is configured in the error status
mode (BISTM = LOW), each of the ROUT[23:0] outputs will
correspond to bit errors on a cycle-by-cycle basis. The result
of bit mismatches are indicated on the respective parallel in-
puts on the ROUT[23:0] data output pins. In the BIST error-
count accumulator mode (BISTM = HIGH), an 8-bit counter
on ROUT[7:0] is used to represent the number of errors de-
tected (0 to 255 max). The successful completion of the BIST
test is reported on the PASS pin on the Deserializer. The
Deserializer's PLL must first be locked to ensure the PASS
status is valid. The PASS status pin will stay LOW and then
DD
=3.3V,
Rpullup=1KΩ,
Figure
Rpulldown=1.2KΩ;
Figure
15). In the PTO Fre-
16) per every 4
Figure
23):
or
19
transition to HIGH once a BER of 1x10
the transmission link.
BACKWARDS COMPATIBLE MODE WITH DS90C241
AND DS90C124
The RAOFF pin allows a backward compatible mode with
DS90C241/DS90C124 devices. To interface with either
DS90C241 Serializer or DS90C124 Deserializer, the RAOFF
pin on DS90UR241 or DS90UR124 must be tied HIGH to dis-
able the additional LSFR coding. For normal operation direct-
ly with DS90UR241 to DS90UR124, RAOFF pins are set
LOW. See
Applications Information
USING THE DS90UR241 AND DS90UR124
The
(SERDES) pair sends 24 bits of parallel LVCMOS data over
a serial LVDS link up to 1.03 Gbps. Serialization of the input
data is accomplished using an on-board PLL at the Serializer
which embeds clock with the data. The Deserializer extracts
the clock/control information from the incoming data stream
and deserializes the data. The Deserializer monitors the in-
coming clock information to determine lock status and will
indicate lock by asserting the LOCK output high.
DISPLAY APPLICATION
The DS90UR241/124 chipset is intended for interface be-
tween a host (graphics processor) and a Display. It supports
an 18-bit color depth (RGB666) and up to 1280 X 480 display
formats. In a RGB666 configuration 18 color bits (R[5:0], G
[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS,
HS and DE) along with three spare bits are supported across
the serial link with PCLK rates from 5 to 43 MHz.
TYPICAL APPLICATION CONNECTION
Figure 18
rializer (SER). The LVDS outputs utilize a 100 ohm termina-
tion and 100nF coupling capacitors to the line. Bypass
capacitors are placed near the power supply pins. At a mini-
mum, three 0.1uF capacitors should be used for local by-
passing. A system GPO (General Purpose Output) controls
the TPWDNB pin. In this application the TRFB pin is tied High
to latch data on the rising edge of the TCLK. The DEN signal
is not used and is tied High also. The application is to the
companion Deserializer (DS90UR124) so the RAOFF pin is
tied low to scramble the data and improve link signal quality.
In this application the link is typical, therefore the VODSEL
pin is tied Low for the standard LVDS swing. The pre-empha-
sis input utilizes a resistor to ground to set the amount of pre-
emphasis desired by the application.
Figure
serializer (DES). The LVDS inputs utilize a 100 ohm termina-
tion and 100nF coupling capacitors to the line. Bypass
capacitors are placed near the power supply pins. At a mini-
mum, four 0.1uF capacitors should be used for local bypass-
ing. A system GPO (General Purpose Output) controls the
RPWDNB pin. In this application the RRFB pin is tied High to
strobe the data on the rising edge of the RCLK. The REN
signal is not used and is tied High also. The application is to
the companion Serializer (DS90UR241) so the RAOFF pin is
tied low to descramble the data. Output (LVCMOS) signal
quality is set by the SLEW pin, and the PTOSEL pin can be
used to reduce simultaneous output switching by introducing
a small amount of delay between output banks.
19shows a typical application of the DS90UR124 De-
DS90UR241/DS90UR124
shows a typical application of the DS90UR241 Se-
Table 1
and
Table 2
for more details.
Serializer/Deserializer
-9
is achieved across
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