PCA9517AD,112 NXP Semiconductors, PCA9517AD,112 Datasheet - Page 5

• Manufacturer Part Number: PCA9517AD,112
• Description: IC I2C BUS REPEATER 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Repeaterr

Specifications of PCA9517AD,112

• Tx/rx Type: I²C Logic
• Delay Time: 170ns
• Capacitance - Input: 6pF
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 5mA
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285763112; PCA9517AD; PCA9517AD

NXP Semiconductors
7. Application design-in information
PCA9517A_2
Product data sheet
A typical application is shown in
on a 3.3 V I
Master devices can be placed on either bus.
The PCA9517A is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
When port A of the PCA9517A is pulled LOW by a driver on the I
detects the falling edge when it goes below 0.3V
port B to turn on, causing port B to pull down to about 0.5 V. When port B of the
PCA9517A falls, first a CMOS hysteresis type input detects the falling edge and causes
the internal driver on port A to turn on and pull the port A pin down to ground. In order to
illustrate what would be seen in a typical application, refer to
bus master in
shown in
transmission except that the HIGH level may be as low as 0.9 V, and the turn on and turn
off of the acknowledge signals are slightly delayed.
On the B bus side of the PCA9517A, the clock and data lines would have a positive offset
from ground equal to the V
be pulled to the V
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9517A for a short delay while the A bus side rises above 0.3V
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9517A (V
recognized by the PCA9517A and then transmitted to the A bus side.
Multiple PCA9517A port A sides can be connected in a star configuration
allowing all nodes to communicate with each other.
Multiple PCA9517As can be connected in series
to port B. I
number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
Fig 4.
Typical application
Figure 8
2
2
C-bus slave devices can be connected to any of the bus segments. The
C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.
Figure 4
OL
MASTER
400 kHz
would be observed on the A bus. This looks like a normal I
BUS
of the slave device which is very close to ground in this example. At
SDA
SCL
were to write to the slave through the PCA9517A, waveforms
Rev. 02 — 5 May 2008
10 k
OL
bus B
3.3 V
of the PCA9517A. After the 8
Figure
10 k
SDAB
SCLB
EN
V
4. In this example, the system master is running
CC(B)
PCA9517A
V
CC(A)
CC(A)
(Figure
SDAA
SCLA
10 k
Level translating I
and causes the internal driver on
6) as long as port A is connected
bus A
1.2 V
th
clock pulse, the data line will
IL
10 k
Figure 8
) be at or below 0.4 V to be
SDA
SCL
2
400 kHz
C-bus, a comparator
SLAVE
CC(A)
002aad468
PCA9517A
and
© NXP B.V. 2008. All rights reserved.
then it continues
2
C-bus repeater
(Figure
Figure
2
C-bus
9. If the
5),
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