DS33Z11+ Maxim Integrated Products, DS33Z11+ Datasheet - Page 100
![IC MAPPER ETHERNET 169-CSBGA](/photos/6/93/69376/169-csbga_21-0354_sml.jpg)
DS33Z11+
Manufacturer Part Number
DS33Z11+
Description
IC MAPPER ETHERNET 169-CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z11.pdf
(172 pages)
Specifications of DS33Z11+
Applications
Data Transport
Interface
SPI/Parallel
Voltage - Supply
1.8V, 3.3V
Package / Case
169-CSBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: X86 Transmit Receive Control (TRSAPIL0-7) This is the address field for the X.86 transmitter and
expected value for the receiver. The register is reset to 0x01
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Committed Information Rate Enable (CIRE) Set this bit to 1 to enable the Committed Information Rate
Controller feature.
Bits 0 – 6: Committed Information Rate (CIR0-6) These bits provide the value for the committed information
rate. The value is multiplied by 500 kbps to get the CIR value. The user must ensure that the CIR value is less
than or equal to the maximum Serial Interface transmit rate. The valid range is from 1 to 104. Any values outside
this range will result in unpredictable behavior. Note that a value of 104 translates to a 52 Mbps line rate. Hence if
the CIR is above the line rate, the rate is not restricted by the CIR. For instance, if using a T1 line and the CIR is
programmed with a value of 104, it has no effect in restricting the rate.
TRSAPIL7
CIRE
7
0
7
0
TRSAPIL6
CIR6
6
0
6
0
LI.TRX86SAPIL
Transmit Receive X.86 SAPIL
0DCh
LI.CIR
Committed Information Rate
0DDh
TRSAPIL5
CIR5
5
0
5
0
TRSAPIL4
100 of 172
CIR4
4
0
4
0
TRSAPIL3
CIR3
3
0
3
0
TRSAPIL2
CIR2
2
0
2
0
TRSAPIL1
CIR1
1
0
1
0
TRSAPIL0
CIR0
0
1
0
1
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