DS33Z11+ Maxim Integrated Products, DS33Z11+ Datasheet - Page 98
![IC MAPPER ETHERNET 169-CSBGA](/photos/6/93/69376/169-csbga_21-0354_sml.jpg)
DS33Z11+
Manufacturer Part Number
DS33Z11+
Description
IC MAPPER ETHERNET 169-CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z11.pdf
(172 pages)
Specifications of DS33Z11+
Applications
Data Transport
Interface
SPI/Parallel
Voltage - Supply
1.8V, 3.3V
Package / Case
169-CSBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Transmit Manual Error Insertion (TMEI) A zero to one transition will insert a single error in the Transmit
direction.
Register Name:
Register Description:
Register Address:
Bit 0: Transmit PMU Update (TPMUU) This signal causes the transmit cell/packet processor block performance
monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to
be updated with the latest data, and the counters reset (0 or 1). This update updates performance monitoring
counters for the Serial Interface.
Register Name:
Register Description:
Register Address:
Bit 0: Transmit PMU Update Status (TPMUS) This bit is set when the Transmit PMU Update is completed. This
bit is cleared when TPMUU is reset.
Bit #
Name
Default
Bit #
Name
Default
7
0
-
7
0
7
0
-
-
LI.THPMUU
Serial Interface Transmit HDLC PMU Update Register
0D6h
LI.THPMUS
Serial Interface Transmit HDLC PMU Update Status Register
0D7h
6
0
-
6
0
6
0
-
-
LI.TMEI
Transmit Manual Error Insertion
0D4h
5
0
-
5
0
5
0
-
-
98 of 172
4
0
-
4
0
4
0
-
-
3
0
-
3
0
3
0
-
-
2
0
-
2
0
2
0
-
-
1
0
-
1
0
1
0
-
-
TPMUU
TPMUS
TMEI
0
0
0
0
0
0
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