DS33Z11+ Maxim Integrated Products, DS33Z11+ Datasheet - Page 142
![IC MAPPER ETHERNET 169-CSBGA](/photos/6/93/69376/169-csbga_21-0354_sml.jpg)
DS33Z11+
Manufacturer Part Number
DS33Z11+
Description
IC MAPPER ETHERNET 169-CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z11.pdf
(172 pages)
Specifications of DS33Z11+
Applications
Data Transport
Interface
SPI/Parallel
Voltage - Supply
1.8V, 3.3V
Package / Case
169-CSBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10 FUNCTIONAL TIMING
10.1 Functional Serial I/O Timing
The Serial Interface provides flexible timing to interconnect with a wide variety of serial interfaces. TDEN is an
input signal that can be used to enable or block the TSER data. The “shaded bits” are not clocked by the
DS33Z11. The TDEN must occur one bit before the effected bit in the TSER stream. Note that polarity of the
TDEN is selectable through LI.TSLCR. In the figure below, TDEN is active low , allowing the bits to clock and
inactive high, causing the next data bit not be clocked. TCLK can be gapped as shown in the following figure.
Similarly, the receiver function is governed by RCLKI, RDEN and RSER. RSER data will not be provided to the
receiver for the bits blocked when RDEN is inactive. The RDEN polarity can be programmed by LI.RSLCR. The
RDEN signal must be coincident with the RSER bit that needs to be blocked.
Figure 10-1 TX Serial Interface Functional Timing
Figure 10-2 RX Serial Interface Functional Timing
RCLK Gapped
TCLK Gapped
RSER
TSER
RCLKI
RDEN
RSER
gapped
TSER
TSER
TCLK
TCLKI
TDEN
TSER
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