DS33Z11+ Maxim Integrated Products, DS33Z11+ Datasheet - Page 103

• Manufacturer Part Number: DS33Z11+
• Description: IC MAPPER ETHERNET 169-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11+

• Applications: Data Transport
• Interface: SPI/Parallel
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 169-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive FCS Errored Packet Latched (REPL) This bit is set when a packet with an errored FCS is
detected.
Bit 6: Receive Aborted Packet Latched (RAPL) This bit is set when a packet with an abort indication is
detected.
Bit 5: Receive Invalid Packet Detected Latched (RIPDL) This bit is set when a packet with a non-integer
number of bytes is detected.
Bit 4: Receive Small Packet Detected Latched (RSPDL) This bit is set when a packet smaller than the
minimum packet size is detected.
Bit 3: Receive Large Packet Detected Latched (RLPDL) This bit is set when a packet larger than the maximum
packet size is detected.
Bit 2: Receive FCS Errored Packet Count Latched (REPCL) This bit is set when the REPC bit in the RPPSR
register transitions from zero to one.
Bit 1: Receive Aborted Packet Count Latched (RAPCL) This bit is set when the RAPC bit in the RPPSR
register transitions from zero to one.
Bit 0: Receive Size Violation Packet Count Latched (RSPCL) This bit is set when the RSPC bit in the RPPSR
register transitions from zero to one.
REPL
7
-
RAPL
6
-
LI.RPPSRL
Receive Packet Processor Status Register Latched
105h
RIPDL
5
-
103 of 172
RSPDL
4
-
RLPDL
3
-
REPCL
2
-
RAPCL
1
-
RSPCL
0
-