PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 53

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5
5.1
PI7C8154A does not have a hardware mechanism to guarantee data synchronization for posted
write transactions. Therefore, all posted write transactions must be followed by a read operation,
either from the device to the location just written (or some other location along the same path), or
from the device driver to one of the device registers.
ERROR HANDLING
PI7C8154A checks, forwards, and generates parity on both the primary and secondary interfaces.
To maintain transparency, PI7C8154A always tries to forward the existing parity condition on one
bus to the other bus, along with address and data. PI7C8154A always attempts to be transparent
when reporting errors, but this is not always possible, given the presence of posted data and
delayed transactions.
To support error reporting on the PCI bus, PI7C8154A implements the following:
This chapter provides detailed information about how PI7C8154A handles errors. It also describes
error status reporting and error operation disabling.
ADDRESS PARITY ERRORS
PI7C8154A checks address parity for all transactions on both buses, for all address and all bus
commands. When PI7C8154A detects an address parity error on the primary interface, the
following events occur:
When PI7C8154A detects an address parity error on the secondary interface, the following events
occur:
The device signaling the interrupt performs a read of the data just written (software).
The device driver performs a read operation to any register in the interrupting device before
accessing data written by the device (software).
System hardware guarantees that write buffers are flushed before interrupts are forwarded.
PERR# and SERR# signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR# event disable register
If the parity error response bit is set in the command register, PI7C8154A does not claim the
transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If
parity error response bit is not set, PI7C8154A proceeds normally and accepts the transaction
if it is directed to or across PI7C8154A.
PI7C8154A sets the detected parity error bit in the status register.
PI7C8154A asserts P_SERR# and sets signaled system error bit in the status register, if both
the following conditions are met:
If the parity error response bit is set in the bridge control register, PI7C8154A does not claim
the transaction with S_DEVSEL#; this may allow the transaction to terminate in a master
The SERR# enable bit is set in the command register
The parity error response bit is set in the command register
Page 53 of 114
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A