PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 72

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10
11
11.1
11.2
12
VITAL PRODUCT DATA (VPD)
The bridge contains the Vital Product Data registers as specified in the PCI Local Bus
Specification, Revision 2.2. The bridge provides 192 bytes of storage in the EEPROM for the VPD
data starting at offset ECh of the configuration space.
CLOCKS
This chapter provides information about the clocks.
PRIMARY AND SECONDARY CLOCK INPUTS
PI7C8154A implements a primary clock input for the PCI interface. The primary interface is
synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to
the secondary clock input. The secondary clock operates at either the same frequency as the
primary clock or at half of the frequency of the primary clock. PI7C8154A operates at a maximum
frequency of 66 MHz.
SECONDARY CLOCK OUTPUTS
The bridge has 10 secondary clock outputs, S_CLKOUT[9:0], that can be used as clock inputs for
up to nine external secondary bus devices. The S_CLKOUT[9:0] outputs are derived from P_CLK.
These are the rules for using secondary clocks:
PCI POWER MANAGEMENT
PI7C8154A incorporates functionality that meets the requirements of the PCI Power Management
Specification, Revision 1.0. These features include:
EEPROM BYTE
Each secondary clock output is limited to no more than one load
One of the secondary clock outputs must be used to feedback to S_CLKIN
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
Support for D0, D3
ADDRESS
29 – 2Ah
2C – 3Fh
21 – 22h
23 – 24h
25 – 26h
27 – 28h
2Bh
HOT
CONFIGURATION
and D3
DE – DFh
OFFSET
E0 – E1h
74 – 75h
80 – 81h
82 – 83h
E3h
COLD
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power management states
Port Option Register
Secondary Master Timeout Counter
Primary Master Timeout Counter
Power Management Capabilities
Power Management Data
DESCRIPTION
Power Management Control Status Register
Reserved – MUST BE SET TO 0
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A