PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 6

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3
4
5
6
7
2.11
3.1
3.2
3.3
3.4
4.1
4.2
4.3
4.4
5.1
5.2
5.3
5.4
6.1
6.2
6.3
7.1
7.2
2.11.1
2.11.2
2.11.3
2.11.3.1
2.11.3.2
2.11.3.3
2.11.4
2.11.4.1
2.11.4.2
2.11.4.3
ADDRESS DECODING ............................................................................................................................43
3.2.1
3.2.2
3.3.1
3.3.2
3.3.3
3.4.1
3.4.2
TRANSACTION ORDERING .................................................................................................................50
ERROR HANDLING ................................................................................................................................53
5.2.1
5.2.2
5.2.3
5.2.4
EXCLUSIVE ACCESS..............................................................................................................................62
6.2.1
6.2.2
PCI BUS ARBITRATION.........................................................................................................................64
7.2.1
7.2.2
7.2.3
TRANSACTION TERMINATION....................................................................................................37
ADDRESS RANGES .........................................................................................................................44
I/O ADDRESS DECODING ..............................................................................................................44
MEMORY ADDRESS DECODING .................................................................................................46
VGA SUPPORT .................................................................................................................................49
TRANSACTIONS GOVERNED BY ORDERING RULES .............................................................50
GENERAL ORDERING GUIDELINES ...........................................................................................51
ORDERING RULES ..........................................................................................................................51
DATA SYNCHRONIZATION ..........................................................................................................52
ADDRESS PARITY ERRORS ..........................................................................................................53
DATA PARITY ERRORS .................................................................................................................54
DATA PARITY ERROR REPORTING ............................................................................................58
SYSTEM ERROR (SERR#) REPORTING .......................................................................................61
CONCURRENT LOCKS ...................................................................................................................62
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8154A ..........................................................62
ENDING EXCLUSIVE ACCESS......................................................................................................64
PRIMARY PCI BUS ARBITRATION ..............................................................................................65
SECONDARY PCI BUS ARBITRATION ........................................................................................65
I/O BASE AND LIMIT ADDRESS REGISTER ..............................................................................45
ISA MODE .....................................................................................................................................45
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS..........................................46
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS...................................47
PREFETCHABLE MEMORY 64-BIT ADDRESSING REGISTERS ..............................................48
VGA MODE ...................................................................................................................................49
VGA SNOOP MODE .....................................................................................................................49
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE...........................54
READ TRANSACTIONS ................................................................................................................54
DELAYED WRITE TRANSACTIONS ............................................................................................55
POSTED WRITE TRANSACTIONS ...............................................................................................57
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION.....................................................62
LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................................64
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER......................................65
PREEMPTION...............................................................................................................................66
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER .......................................67
MASTER TERMINATION INITIATED BY PI7C8154A............................................................38
MASTER ABORT RECEIVED BY PI7C8154A .........................................................................38
TARGET TERMINATION RECEIVED BY PI7C8154A............................................................39
DELAYED WRITE TARGET TERMINATION RESPONSE ......................................................39
POSTED WRITE TARGET TERMINATION RESPONSE.........................................................41
DELAYED READ TARGET TERMINATION RESPONSE .......................................................41
TARGET TERMINATION INITIATED BY PI7C8154A ............................................................42
TARGET RETRY .......................................................................................................................42
TARGET DISCONNECT...........................................................................................................43
TARGET ABORT.......................................................................................................................43
Page 6 of 112
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A