PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 94

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.46
14.1.47
P_SERR# STATUS REGISTER – OFFSET 68h
PORT OPTION REGISTER – OFFSET 74h
Bit
16
17
18
19
20
21
22
23
31:24
Bit
0
1
2
3
Function
Address Parity
Error
Posted Write
Data Parity Error
Posted Write
Non-delivery
Target Abort
during Posted
Write
Master Abort
during Posted
Write
Delayed Write
Non-delivery
Delayed Read –
No Data from
Target
Delayed
Transaction
Master Timeout
Reserved
Function
Reserved
Primary Memory
Read Command
Alias Enable
Primary Memory
Write Command
Alias Enable
Secondary
Memory Read
Command Alias
Enable
Type
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/O
Type
R/O
R/W
R/W
R/W
Page 94 of 114
Description
1: Signal P_SERR# was asserted because an address parity error was
detected on P or S bus.
Reset to 0
1: Signal P_SERR# was asserted because a posted write data parity error
was detected on the target bus.
Reset to 0
1: Signal P_SERR# was asserted because the bridge was unable to deliver
post memory write data to the target after 2
Reset to 0
1: Signal P_SERR# was asserted because the bridge received a target
abort when delivering post memory write data.
Reset to 0.
1: Signal P_SERR# was asserted because the bridge received a master
abort when attempting to deliver post memory write data
Reset to 0.
1: Signal P_SERR# was asserted because the bridge was unable to deliver
delayed write data after 2
Reset to 0
1: Signal P_SERR# was asserted because the bridge was unable to read
any data from the target after 2
Reset to 0.
1: Signal P_SERR# was asserted because a master did not repeat a read or
write transaction before master timeout.
Reset to 0.
Returns 0 when read. Reset to 0
Description
Returns 0 when read. Reset to 0.
0: exact matching for non-posted memory write retry cycles from initiator
on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry cycles
from the initiator on the primary interface
Reset to 1
Reserved
Reset to 0
0: exact matching for memory read retry cycles from initiator on the
secondary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry cycles
from initiator on the secondary interface
Reset to 1
24
attempts.
24
attempts.
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
24
attempts.
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A