MT46V64M8P-5B:J Micron Technology Inc, MT46V64M8P-5B:J Datasheet - Page 75

• Manufacturer Part Number: MT46V64M8P-5B:J
• Description: IC SDRAM 512MB 200MHZ 66TSOP
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT46V64M8P-5B:J

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP (0.400", 10.16mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles
after the first WRITE command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Figure 40 on page 77 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 41 on page 78. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 42 on page 78.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst,
on page 79.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 44 on page 80.
Note that only the data-in pairs that are registered prior to the
to the internal array, and any subsequent data-in should be masked with DM, as shown
in Figure 45 on page 81.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst,
Figure 46 on page 82.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 47 on page 83 and Figure 48 on page 84. Only the data-in pairs regis-
tered prior to the
should be masked with DM, as shown in Figures 47 and 48. After the PRECHARGE
command, a subsequent command to the same bank cannot be issued until
t
WR period are written to the internal array; any subsequent data-in
75
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WTR should be met, as shown in Figure 43
512Mb: x4, x8, x16 DDR SDRAM
t
WR should be met, as shown in
©2000 Micron Technology, Inc. All rights reserved.
t
WTR period are written
Operations
t
RP is met.