MT41J64M16JT-187E:G Micron Technology Inc, MT41J64M16JT-187E:G Datasheet - Page 161

• Manufacturer Part Number: MT41J64M16JT-187E:G
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT41J64M16JT-187E:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 96-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 75:
Table 76:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_5.fm - Rev. F 11/08 EN
Symbol
ODTL on
ODTL off
t
t
ODTH4
ODTH8
t
t
AONPD
AOFPD
AON
AOF
MR1[9, 6, 2]
110 and 111
000–101
000–101
000
000
Truth Table – ODT (Nominal)
Note 1 applies to the entire table
ODT Parameter
ODT minimum HIGH time after ODT
ODT turn-off relative to ODTL off
ODT asynchronous turn off delay
ODT turn-on relative to ODTL on
ODT asynchronous turn on delay
ODT synchronous turn off delay
ODT synchronous turn on delay
ODT minimum HIGH time after
Notes:
assertion or write (BC4)
ODT Pin
Description
completion
completion
write (BL8)
X
0
1
0
1
1. Assumes dynamic ODT is disabled (see "Dynamic ODT" on page 162 when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal to
3. ODT must be disabled during reads. The R
Nominal ODT resistance R
page 61. The R
mentioned. DDR3 SDRAM supports multiple R
can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. R
the DRAM is initialized, calibrated, and not performing read access or when it is not in
self refresh mode.
Write accesses use R
during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 78 on page 163).
ODT timings are summarized in Table 76, as well as listed in Table 53 on page 67.
Examples of nominal ODT timing are shown in conjunction with the synchronous mode
of operation in “Synchronous ODT Mode” on page 167.
have it off during writes.
ODT is applicable if enabled.
R
TT
DRAM Termination State
R
R
_
R
R
NOM
TT
TT
TT
TT
TT
_
_
_
_
NOM
_
NOM
NOM
NOM
NOM
reserved, ODT on or off
TT
enabled, ODT off
disabled, ODT off
enabled, ODT on
disabled, ODT on
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
or write registration
_
termination value applies to the output pins previously
Write registration
NOM
with ODT HIGH
with ODT HIGH
Completion of
Completion of
TT
Begins at
ODTL off
ODTL on
if dynamic ODT (R
_
161
NOM
is defined by MR1[9, 6, 2], as shown in Figure 47 on
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TT
TT
_
ODT registered
ODT registered
_
NOM
R
R
NOM
Defined to
TT
TT
Any valid except self refresh, read
Any valid except self refresh, read
_
_
TT
R
R
TT
R
R
ON
OFF
1Gb: x4, x8, x16 DDR3 SDRAM
TT
LOW
LOW
TT
TT
TT
termination is allowed any time after
value is restricted during writes. Dynamic
_
_
_
_
NOM
_
_
WR
±
OFF
OFF
±
ON
ON
t
t
AON
AOF
) is disabled. If R
On-Die Termination (ODT)
values based on RZQ/n where n
DRAM State
Any valid
Any valid
Illegal
Definition for All
DDR3 Speed Bins
©2006 Micron Technology, Inc. All rights reserved.
See Table 53 on
0.5
CWL + AL - 2
CWL + AL - 2
t
page 67
CK ± 0.2
6
4
1–9
1–9
t
t
CK
CK
TT
_
NOM
t
CK
is used
Notes
Units
t
t
t
t
t
2
3
2
3
ns
ns
ps
CK
CK
CK
CK
CK