BD9740KN-E2 Rohm Semiconductor, BD9740KN-E2 Datasheet - Page 7

• Manufacturer Part Number: BD9740KN-E2
• Description: IC SWITCH REG W/FET 48UQFN
• Manufacturer: Rohm Semiconductor
• Series: -r
• Type: Step-Down (Buck), Step-Up (Boost), Inverting, PWMr

Specifications of BD9740KN-E2

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 7
• Voltage - Output: -
• Current - Output: 30mA
• Frequency - Switching: 100kHz ~ 1.2MHz
• Voltage - Input: 1.5 V ~ 10 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

●BD9739KN Pin No.
●BD9740KN Pin No.
●Block diagram explanation and setting peripheral IC components
BD9739KN,BD9740KN
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www.rohm.com
1. Voltage reference (VREF)
2. REGA
3. UDSEL
4. On/off logic
5. Setting the short protection detection time
VREF is the reference voltage source of 1.0V output voltage.
Connect a capacitor to prevent oscillation. Set the capacitance from 1.0 μF to 10 μF.
REGA and REGD are regulators with output voltages of 2.5 V. REGA is used as the power supply for the IC's internal
blocks.Connect a capacitor to prevent oscillation. Set the capacitance from 4.7 μ to 10 μF.
To enable step-up mode, connect VCC to the UDSEL pin. To enable step-up mode connect 0V to the UDSEL pin.
When using the startup circuit, set the pin to step-up mode. Because the pin uses COMS inverter input, you must connect
the pin to either GND or VCC in order to prevent undefined input.
The voltage applied to the STB pins can be controlled whether each channel is on or off.
CH1, CH4, and CH5 can be controlled independently, while CH2 and CH3 can be controlled simultaneously.
Applying a voltage of over 2 V turns on the corresponding channel(s), while leaving the pin open or applying 0 V turns off
the corresponding channel(s).
Turning off all channels causes the IC to be in a standby state.
Each pin is connected to GND by a 400 k pull-down resistor.
The detection time can be set when the capacitor is connected to the SCP pin.
When the detection time is reached, the latch circuit operates, turning off the output for all channels.
To reset the latch circuit, turn all STB pins off, and then back on again.
*Set the capacitor that is connected to the SCP pin from 0.001 μF to 2.2 μF.
40,41,45,47,48
51,52,53
Pin No.
Pin No.
8,9,57
Detection time (sec) = CSCP  VTSC / ISCP
(CSCP: capacitance; VTSC: SCP pin detection voltage, ISCP: SCP pin source current)
6,7
61
29
54
14
59
42
30
58
21
46
10
42
31
22
4
PGND23,PGND
OUT1,3,5,6,7
OUT4,5,6
Pin name
Pin name
PVCCH
VREGA
PVCCH
PGND4
VREGA
PVCCL
OUT7B
PGND
PVCC
PVCC
VBAT
VBAT
GND
GND
VCC
VCC
26,24,21,47,46,41,39
16,18,27,28,32,35,36
27,23,22,48,45,40
15,19,26,29,33,34
4,5,12,13
6,7,10,11
Pin No.
Pin No.
3,38,39
37,38
60
55
56
35
43
44
43
20
5
9
8
7/14
INV7I,INV7V
DRAIN2,3H
DRAIN2,3L
INV 1～5,7
DTC 5～7
DRAIN4H
Pin name
Pin name
DRAIN4L
INV 1～6
FB 1～7
FB 1～7
OUT1M
OUT1B
OUT1S
OUT1B
MAIN2
DTC 5
VREF
SUB2
VREF
15,16,17,18,19,20
11,12,13,14
31,49,3,63
Pin No.
50,2,62
Pin No.
44,36
30,37
1,64
28
25
34
32
23
24
25
33
17
1
2
Technical Note
2010.09 - Rev.A
STB 1,23,4,5,6,7
SWOUT 1,4,6,7
STB1,234,56,7
NON6,NON7
SWIN4,6,7
UDSEL1,5
UDSEL12
Pin name
Pin name
UDSEL3
NON5,7
SS23
SCP
SCP
SS1
SS1
RT
CT
RT
CT