BD9740KN-E2 Rohm Semiconductor, BD9740KN-E2 Datasheet - Page 8

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BD9740KN-E2

Manufacturer Part Number
BD9740KN-E2
Description
IC SWITCH REG W/FET 48UQFN
Manufacturer
Rohm Semiconductor
Series
-r
Type
Step-Down (Buck), Step-Up (Boost), Inverting, PWMr
Datasheet

Specifications of BD9740KN-E2

Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
7
Voltage - Output
-
Current - Output
30mA
Frequency - Switching
100kHz ~ 1.2MHz
Voltage - Input
1.5 V ~ 10 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
BD9739KN,BD9740KN
© 2010 ROHM Co., Ltd. All rights reserved.
www.rohm.com
6. Setting the oscillating frequency
7. Startup channel soft-start operation
8. SWOUT1 pin (BD9734KN/BD9738KN/BD9739KN)
9. Soft start operation depending on SS pins (BD9739KN)
The oscillating frequency can be set by connecting the resistance value to the RT pin and connecting the capacitance
value to the CT pin.
Oscillating frequency = VRT / (CT  RT) (Unit: Hz)
*Set the resistance value, connected to the RT pin, from 4.7 k to 30 k
*Set the capacitance value, connected to the CT pin, from 100 pF to 10,000 pF.
Fig. 4 Oscillating Frequency Versus RT Pin Resistance
The startup channel's soft start can be controlled by the capacitor connected to the SS1 pin.
Times can be determined with the following equation:
Startup time (sec) = (VSS / ISS)  CSS
(VSS = SS pin voltage [= 0.7 V], ISS = soft start charge current [= approximately 2.0 μA]; CSS = capacitor capacitance)
*Set the capacitance value, connected to the SS1 pin, from 0.001 μF to 2.2 μF.
To prevent current from flowing from VOUT1 to the feedback resistor, during standby operation, connect the ground side of
CH1's feedback resistor to SWOUT1.
Soft start operation for CH2 and CH3 can be controlled by the capacitor connected to the SS23 pins.
Times can be determined with the following equation:Startup time (sec) = (VSS / ISS)  CSS23
(VSS: SS pin voltage [= 1.0 V]; ISS: soft start charge current [= approximately 10 μA]; CSS: capacitance)
*Startup of CH2 begins when CH3 output reaches approximately 70%.
*Set the capacitance value, connected to each SS23 pin, from 0.005 μF to 1.0 μF.
Fig. 6 Startup Channel Startup Waveform
(VRT: RT pin voltage; CT: OSC timing capacitance; RT: OSC timing resistance)
Example: When CSS = 0.01 μF, startup time = 0.7 / (2.0 10-6)  (0.01  10-6) = 3.5 ms
1000
100
VCC output voltage waveform
(Reference Data)
10
RT pin RESISTANCE[k]
SS pin voltage
waveform
100pF
330pF
180pF
100
Fig. 8 DTC External Setting Circuit
RB
RA
VREGA
DTC
DRAIN1L
STBY1
VREGA
OUT1B
R2
R1
SS1
VCC
8/14
VREGA
Fig. 5 Oscillating Frequency Versus CT Pin Capacitance
Approximately
30 k
Approximately
93 k
(Startup block Main)
Startup OSC
(approximately 100 kHz)
(Startup block repeat
oscillation prohibited)
Approximately
0.5 V
1000
100
Fig. 7 Timing Chart
100
CT pin CAPACITANCE [pF]
Approximately 0.7 V
OSC
Approximately 1.0 V
30kΩ
VREF=1.0 V
11kΩ
20kΩ
VREGA
VCC
Technical Note
1000
2010.09 - Rev.A
FB

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