ADP5033ACBZ-1-R7 Analog Devices Inc, ADP5033ACBZ-1-R7 Datasheet - Page 17

• Manufacturer Part Number: ADP5033ACBZ-1-R7
• Description: IC REG QD SYNC BUCK/LDO1 16WLCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADP5033ACBZ-1-R7

• Topology: Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
• Function: Any Function
• Number Of Outputs: 4
• Frequency - Switching: 3MHz
• Voltage/current - Output 1: 0.8 V ~ 3.3 V, 800mA
• Voltage/current - Output 2: 0.8 V ~ 3.3 V, 800mA
• Voltage/current - Output 3: 0.8 V ~ 3.3 V, 300mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-WFBGA, WLCSP
• No. Of Outputs: 4
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +125°C
• Supply Voltage: 5.5V
• No. Of Step-down Dc - Dc Converters: 2
• No. Of Ldo Regulators: 2
• Digital Ic Case Style: WLCSP
• No. Of Regulated Outputs: 2
• Rohs Compliant: Yes
• Primary Input Voltage: 5.5V
• Output Voltage: 2.8V
• Output Current: 800mA
• Switching Frequency Max: 3MHz
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: ADP5033ACBZ-1-R7TR

THEORY OF OPERATION
PGND1
POWER MANAGEMENT UNIT
The ADP5033 is a micropower management unit (μPMU)
combing two step-down (buck) dc-to-dc convertors and two
low dropout linear regulators (LDO). The high switching
frequency and tiny 16-ball WLCSP package allow for a small
power management solution.
To combine these high performance regulators into the μPMU,
there is a system controller allowing them to operate together.
The buck regulators can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
buck switching frequency is always constant and does not
change with the load current. If the MODE pin is at logic low,
the switching regulators operate in auto PWM/PSM mode.
In this mode, the regulators operate at fixed PWM frequency
when the load current is above the power saving current thresh-
old. When the load current falls below the power save current
threshold, the regulator in question enters PSM where the
switching occurs in bursts. The burst repetition is a
VIN1
SW1
ENA
ENB
AND MODE
CONTROL
ENABLE
VDDA
ANTISHOOT
THROUGH
DRIVER
ENBK1
ENBK2
ENLDO1
ENLDO2
PWM
COMP
I
LOW
CURRENT
LIMIT
AND
VDDA
GM ERROR
CONTROL
BUCK1
PWM/
PSM
VIN3
AMP
SOFT START
UNDERVOLTAGE
COMP
ENBK1
LOCK OUT
PSM
LDO
CONTROL
Figure 43. Functional Block Diagram
LDO
75Ω
Rev. 0 | Page 17 of 28
UNDERVOLTAGE
VOUT1
OSCILLATOR
SHUTDOWN
LOCKOUT
THERMAL
SYSTEM
VOUT2
AGND VOUT3
R1
R2
function of the current load and the output capacitor value.
This operating mode reduces the switching and quiescent cur-
rent losses. The auto PWM/PSM mode transition is controlled
independently for each buck regulator. The two bucks operate
synchronized to each other.
When a regulator is turned on, the output voltage ramp is
controlled through a soft start circuit to avoid a large inrush
current due to the charging of the output capacitors.
Thermal Protection
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off all the regulators. Extreme
junction temperatures can be the result of high current opera-
tion, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included so that when thermal shutdown
occurs, the regulators do not return to operation until the on-chip
temperature drops below 130°C. When coming out of thermal
shutdown, all regulators restart with soft start control.
75Ω
ENBK2
PSM
COMP
SOFT START
VIN4
VDDA
600Ω
GM ERROR
AMP
CONTROL
UNDERVOLTAGE
BUCK2
PWM/
PSM
LOCK OUT
LDO
CONTROL
ENLDO1
SEL
OPMODE
Y
LDO
B
A
CURRENT
ANTISHOOT
MODE2
THROUGH
DRIVER
COMP
AND
PWM
I
LOW
LIMIT
ENLDO1
ADP5033
600Ω
R3
R4
VOUT4
ADP5033
VIN2
SW2
PGND2
MODE