PDI1394P25BD ST-Ericsson Inc, PDI1394P25BD Datasheet - Page 33

• Manufacturer Part Number: PDI1394P25BD
• Description: IC IEEE 1394 LINK CTRLR 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of PDI1394P25BD

• Applications: AV,TV, VTR
• Interface: IEEE 1394
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 64-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
18.4 Transmit
When the LLC issues a bus request through the LREQ terminal, the
PHY arbitrates to gain control of the bus. If the PHY wins arbitration
for the serial bus, the PHY-LLC interface bus is granted to the link by
asserting the Grant state (11b) on the CTL terminals for one
SYSCLK cycle, followed by Idle for one clock cycle. The LLC then
takes control of the bus by asserting either Idle (00b), Hold (01b), or
Transmit (10b) on the CTL terminals. Unless the LLC is immediately
releasing the interface, the link may assert the Idle state for at most
one clock before it must assert either Hold or Transmit on the CTL
terminals. The Hold state is used by the LLC to retain control of the
bus while it prepares data for transmission. The LLC may assert
Hold for zero or more clock cycles (i.e., the LLC need not assert
Hold before Transmit). The PHY asserts data-prefix on the serial
bus during this time.
When the LLC is ready to send data, the LLC asserts Transmit on
the CTL terminals as well as sending the first bits of packet data on
the D lines. The Transmit state is held on the CTL terminals until the
last bits of data have been sent. The LLC then asserts either Hold or
Idle on the CTL terminals for one clock cycle and then asserts Idle
for one additional cycle before releasing the interface bus and
putting the CTL and D terminals in a high-impedance state. The
PHY then regains control of the interface bus.
The Hold state asserted at the end of packet transmission indicates
to the PHY that the LLC requests to send another packet
(concatenated packet) without releasing the serial bus. The PHY
responds to this concatenation request by waiting the required
minimum packet separation time and then asserting Grant as
before. This function may be used to send a unified response after
sending an acknowledge, or to send consecutive isochronous
packets during a single isochronous period. Unless multi-speed
concatenation is enabled, all packets transmitted during a single bus
ownership must be of the same speed (since the speed of the
packet is set before the first packet). If multi-speed concatenation is
enabled (when the EMSC bit of PHY register 5 is set), the LLC must
specify the speed code of the next concatenated packet on the D
terminals when it asserts Hold on the CTL terminals at the end of a
packet. The encoding for this speed code is the same as the speed
code that precedes received packet data as given in Table 19.
After sending the last packet for the current bus ownership, the LLC
releases the bus by asserting Idle on the CTL terminals for two clock
cycles. The PHY begins asserting Idle on the CTL terminals one
clock after sampling Idle from the link. Note that whenever the D and
NOTE: SPD = Speed code; see Table 19; d0–dn = Packet data.
2001 Sep 06
1-port 400 Mbps physical layer interface
CTL0, CTL1
SYSCLK
D0–D7
00
11
00
00
(a)
Figure 18. Normal Packet Transmission Timing
00
(b)
00
01
(c)
32
PHY High-impedance Ctl and D Outputs
CTL terminals change direction between the PHY and the LLC,
there is an extra clock period allowed so that both sides of the
interface can operate on registered versions of the interface signals.
The sequence of events for a normal packet transmission is as
follows:
Transmit operation initiated. The PHY asserts grant on the CTL
lines followed by Idle to hand over control of the interface to the
link so that the link may transmit a packet. The PHY releases
control of the interface (i.e., it 3-States the CTL and D outputs)
following the idle cycle.
Optional idle cycle. The link may assert at most one idle cycle
preceding assertion of either hold or transmit. This idle cycle is
optional; the link is not required to assert Idle preceding either
hold or transmit.
Optional hold cycles. The link may assert hold for up to 47 cycles
preceding assertion of transmit. These hold cycle(s) are optional;
the link is not required to assert hold preceding transmit.
Transmit data. When data is ready to be transmitted, the link
asserts transmit on the CTL lines along with the data on the D
lines.
Transmit operation terminated. The transmit operation is
terminated by the link asserting hold or idle on the CTL lines the
link asserts hold to indicate that the PHY is to retain control of the
serial bus in order to transmit a concatenated packet. the link
asserts idle to indicate that packet transmission is complete and
the PHY may release the serial bus. The link then asserts Idle for
one more cycle following this cycle of hold or idle before releasing
the interface and returning control the the PHY.
Concatenated packet speed-code. If multi-speed concatenation is
enabled in the PHY, the link shall assert a speed-code on the D
lines when it asserts Hold to terminate packet transmission. This
speed-code indicates the transmission speed for the
concatenated packet that is to follow. The encoding for this
concatenated packet speed-code is the same as the encoding for
the received packet speed-code (see Table 19). the link may not
concatenate an S100 packet onto any higher speed packet.
After regaining control of the interface, the PHY shall assert at
least one cycle of idle before any subsequent status transfer,
receive operation, or transmit operation.
Link Controls Ctl and D
d0, d1, ...
(d)
10
dn
SPD
00
01
00
(f)
PDI1394P25
(e)
00
00
Preliminary data
SV01762
00
00
(g)