MT49H16M36BM-33:A Micron Technology Inc, MT49H16M36BM-33:A Datasheet - Page 18

• Manufacturer Part Number: MT49H16M36BM-33:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M36BM-33:A

• Organization: 16Mx36
• Address Bus: 23b
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 6:
PDF: 09005aef80fe62fb/Source: 09005aef809f284b
576Mb_RLDRAM_II_CIO_D2.fm - Rev. I 12/10 EN
Operating burst
read current
example
Operating burst
read current
example
Description
I
DD
Operating Conditions and Maximum Limits – Rev. B
BL = 4; Cyclic bank access; Half of address bits
change every two clock cycles; Continuous
data; Measurement is taken during continuous
READ
BL = 8; Cyclic bank access; Half of address bits
change every four clock cycles; Continuous
data; Measurement is taken during continuous
READ
Notes:
1. I
2.
3. Input slew rate is specified in Table 9 on page 20.
4. Definitions for I
5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transi-
6. I
7. Tests for AC timing, I
8. I
4b. HIGH is defined as V
4d. Floating is defined as inputs at V
4g. Sequential bank access is defined as the bank address incrementing by one every
4h. Cyclic bank access is defined as the bank address incrementing by one for each com-
4a. LOW is defined as V
4e. Continuous data is defined as half the DQ signals changing between HIGH and LOW
4c. Stable is defined as inputs remaining at a HIGH or LOW level.
4f. Continuous address is defined as half the address signals changing between HIGH and
≤ V
t
tions more than once per clock cycle.
inal reference/supply voltage levels, but the related specifications and device operations are
tested for the full voltage range specified.
is still referenced to V
are tested for the specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 2 V/ns in the range between V
V
DD
DD
DD
CK =
IH(AC)
DD
every half clock cycle (twice per clock).
LOW every clock cycle (once per clock).
mand access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for
BL = 8 this is every fourth clock.
specifications are tested after the device is properly initialized. +0°C ≤ T
parameters are specified with ODT disabled.
tests may use a V
576Mb: x9, x18, x36 2.5V V
Condition
t
≤ +1.9V, +2.38V ≤ V
DK = MIN,
.
DD
t
RC = MIN.
conditions:
IL
DD
REF
-to-V
IN
, and electrical AC and DC characteristics may be conducted at nom-
IN
(or to the crossing point for CK/CK#), and parameter specifications
EXT
≤ V
≥ V
IH
18
IL(AC)
IH(AC)
≤ +2.63V, +1.4V ≤ V
swing of up to 1.5V in the test environment, but input timing
MAX.
MIN.
REF
I
I
DD4R
DD8R
I
I
DD4R
DD8R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
= V
I
I
DD4R
DD8R
Symbol
EXT
(V
(V
DDQ
(V
(V
DD
DD
(V
(V
DD
DD
, 1.8V V
/2.
) x9/x18
) x9/x18
EXT
EXT
) x36
) x36
DDQ
Electrical Specifications – I
)
)
≤ V
DD
DD
TBD
TBD
TBD
TBD
TBD
TBD
-18
, V
, HSTL, CIO, RLDRAM II
REF
©2004 Micron Technology, Inc. All rights reserved.
-25E
TBD
TBD
TBD
TBD
TBD
TBD
= V
DDQ
TBD
TBD
TBD
TBD
TBD
TBD
/2.
-25
C
≤ +95°C; +1.7V
TBD
TBD
TBD
TBD
TBD
TBD
-33
IL(AC)
t
Units
RC.
mA
mA
and
DD