HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 3
HSDC-JAKIT1W2/DB
Manufacturer Part Number
HSDC-JAKIT1W2/DB
Description
DAC/ADC LATTICE KIT
Manufacturer
NXP Semiconductors
Series
-r
Datasheets
1.ADC1413D125HNC15.pdf
(43 pages)
2.DAC1408D650HNC15.pdf
(98 pages)
3.HSDC-JAKIT1W2DB.pdf
(2 pages)
4.HSDC-JAKIT1W2DB.pdf
(2 pages)
5.HSDC-JAKIT1W2DB.pdf
(3 pages)
Specifications of HSDC-JAKIT1W2/DB
Main Purpose
Interface, ADC/DAC for Lattice ECP3 FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADC1413D, DAC1408D, ECP3 FPGA
Primary Attributes
Loop Back Demo with 2 High Speed Converters
Secondary Attributes
USB Powered
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6898
The DAC1408D650W2/DB is a 14bit dual channel, 2x, 4x and 8x interpolating DAC demonstration board
equipped with JESD204A interface and suitable for dynamic performance evaluation from low to high
output frequency signals sampling up to 650Msps. This demo board features Lattice Semiconductors’
ECP3 FPGA and can be used for functional demonstration, as well as JESD204A interoperability testing
and verification between the DAC1408D650 and the ECP3 FPGA.
Key Features:
Demo box content:
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SW interface to easily program DAC parameters (NCO, Offset, interpolation factor, PLL…) and
download waveforms to ECP3 FPGA
SMA connector for DAC external clock input signal
On board clock generator for DAC and FPGA
On Board ECP3 FPGA enabling data generation:
USB Powered – no external supply required
USB cable
CDROM (LabVIEW user software, datasheets, PCB layout/schematics, drivers, Quick Start Guide)
o Single/ multi Tone for SFDR evaluation
o Test pattern generation for ACLR measurements ( 2/4 carriers WCDMA, TDSCDMA,
GSM‐MC ... Etc )