HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet

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DAC1408D650 Dual 14-bit DAC 650 Msps; 2, 4 or 8 interpolating with JESD204A interface Rev. 4 — 26 November 2010 1. General description The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2, 4 ...

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... NXP Semiconductors  Two’s complement or binary offset data format  LMF = 421 or LMF = 211 support  Differential CML receiver with embedded termination  Synchronization of multiple DAC outputs 3. Applications  Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA  Communication: LMDS/MMDS, point-to-point  ...

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Block diagram SDO SDIO SPI CONTROL REGISTERS SYNC_OUTP DIGITAL LAYER PROCESSING SYNC_OUTN JESD204A VIN_P0 LANE L0 PROC VIN_N0 VIN_P1 LANE L1 PROC VIN_N1 VIN_P2 LANE L2 PROC VIN_N2 VIN_P3 LANE L3 PROC VIN_N3 CLOCK GENERATOR UNIT CLKINP CLKINN Fig ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol SDO SDIO SCLK V DDD(1V8) SCS_N RESET_N n.c. VIRES GAPOUT V DDA(1V8) V DDA(1V8) DAC1408D650 Product data sheet terminal 1 index area 1 SDO SDIO 2 SCLK DDD(1V8) SCS_N 5 6 RESET_N 7 n.c. VIRES 8 DAC1408D650HN GAPOUT ...

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... NXP Semiconductors Table 2. Symbol AGND AUXBN AUXBP V DDA(3V3) AGND V DDA(1V8) AGND V DDA(1V8) V DDA(1V8) AGND IOUTBN IOUTBP AGND AGND IOUTAP IOUTAN AGND V DDA(1V8) V DDA(1V8) AGND V DDA(1V8) AGND V DDA(3V3) AUXAP AUXAN AGND V DDA(1V8) V DDA(1V8) AGND CLKINP CLKINN AGND V DDA(1V8) MDS_P MDS_N V DDD(1V8) n.c. ...

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... NXP Semiconductors Table 2. Symbol VIN_N0 VIN_P0 V DDD(1V8) VIN_P1 VIN_N1 VIN_N2 VIN_P2 V DDD(1V8) VIN_P3 VIN_N3 n.c. n.c. JTAG GND [1] P: power supply; G: ground; I: input; O: output. [ heatsink (exposed die pad to be soldered to GND. A minimum of 81 thermal vias are required). 7. Limiting values Table 3. In accordance with the Absolute Maximum Rating System (IEC 60134). ...

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... NXP Semiconductors 9. Characteristics Table 5. Characteristics 1 1 DDA(1V8) DDD  +85 C; typical values measured at V maximum sample rate; PLL off unless otherwise specified. Symbol Parameter V analog supply voltage DDA(3V3) (3 digital supply voltage DDD(1V8) (1 analog supply voltage DDA(1V8) (1 analog supply current DDA(3V3) (3.3 V) ...

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... NXP Semiconductors Table 5. Characteristics …continued 1 1 DDA(1V8) DDD  +85 C; typical values measured at V maximum sample rate; PLL off unless otherwise specified. Symbol Parameter V input differential idth threshold voltage R input resistance i C input capacitance I Digital inputs (SDIO, SCLK, SCS_N, RESET_N) V LOW-level input ...

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... NXP Semiconductors Table 5. Characteristics …continued 1 1 DDA(1V8) DDD  +85 C; typical values measured at V maximum sample rate; PLL off unless otherwise specified. Symbol Parameter Analog outputs (IOUTAP, IOUTAN, IOUTBP, IOUTBN) I full-scale output O(fs) current V output voltage O R output resistance o C output capacitance o  ...

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... NXP Semiconductors Table 5. Characteristics …continued 1 1 DDA(1V8) DDD  +85 C; typical values measured at V maximum sample rate; PLL off unless otherwise specified. Symbol Parameter f step frequency step Dynamic performances SFDR spurious-free dynamic range SFDR restricted bandwidth RBW spurious-free dynamic range IMD3 ...

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... NXP Semiconductors Table 5. Characteristics …continued 1 1 DDA(1V8) DDD  +85 C; typical values measured at V maximum sample rate; PLL off unless otherwise specified. Symbol Parameter NSD noise spectral density [ guaranteed by design guaranteed by characterization 100 % industrially tested. [2] Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It reflects the delay required by DAC1408D650 to lock to a JESD204A stream ...

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... NXP Semiconductors This device is MCDA-ML compliant, offering inter-lane alignment between several devices. Samples alignment between devices is maintained up to output level because of an NXP proprietary mechanism. One device is configured as the master and all the others are configured as slaves. These align their output samples automatically to the master ones ...

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... NXP Semiconductors 10.2.1 Lane input Each lane is CML compliant terminated to a common voltage with an integrated 50  resistor. Fig 4. The common-mode voltage is programmable by the SET_VCM_VOLTAGE register as shown in DC coupling is only possible if both the DAC and the transmitter have the same common-mode voltage. If this is not the case, AC coupling is required. ...

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... NXP Semiconductors The lane processing makes use of the sync patterns to synchronize the data stream, determine the initial running disparity and extract the 10-bit word from the incoming data stream (word-alignment). The SYNC_OUT signal is also used during normal operation by the DAC1408D650 to request a link reinitialization. This occurs when the 10b/8b module loses synchronization. ...

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... NXP Semiconductors 10.2.4 Descrambler The descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 10.2.5 inter-lane alignment This feature removes strict PCB design skew compensation between the lanes. 10.2.5.1 Single device operation This module handles the alignment of the four data streams. Because of inter-lane skew and each PLL per lane concept, these alignment characters may be received at different times by the receivers ...

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... NXP Semiconductors Fig 7. Each DAC device of the system generates its own reference (ref_A in If configured as a slave, an early-late comparator compares the internal reference with the external reference provided by the MDS pins. The comparator controls an internal buffer that is used to delay the samples. ...

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... NXP Semiconductors 10.2.5.3 Master/slave mode The external reference is provided by one of the DACs (the master DAC), which has to be configured to do this. The others are set to slave mode. TX Fig 8. DAC1408D650 Product data sheet ref_A DIG SYNC_0 ref_A DIG SYNC_1 ref_A DIG SYNC_2 Master-slave mode All information provided in this document is subject to legal disclaimers ...

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... NXP Semiconductors The MDS signal generated by the master DAC must reach all slaves within one DAC output clock period. This induces PCB layout constraints for the MDS signal and also for the clock distribution. Because trace lengths differ, the clock edges reach each of the DACs at different times ...

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... NXP Semiconductors Fig 10. Clock skew case 2: Master is closest The worst case clock skew is given by The minimum allowable trace delay for the MDS signal is given by In real applications, the master DAC can be anywhere and both conditions must be satisfied: Example: clock generator skew =  • ...

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... NXP Semiconductors 10.2.5.4 All slave mode The external reference is provided by the JESD204A transmitter. All DACs are configured in slave mode. INSERTION Fig 11. All slave mode The MDS signal is now driven from the transmitter generated at the end of the inter-lane alignment phase (see the JESD204A standard for details). ...

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... NXP Semiconductors 10.2.6 Frame assembly DAC1408D650 supports only / which means that every frame clock period carries one byte per lane. Frame assembly combines the octet of lane_0 with the six MSB bits of lane_1 and reassembles the original 14-bit sample. The same is done for lane_2 and lane_3 ...

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... NXP Semiconductors SERIAL CLOCK 3.125 GHz Fig 12. Frame assembly DAC1408D650 Product data sheet CHARACTER CLOCK 312.5 MHz encoded octet scrambled b9 / lane 0 encoded octet scrambled b9 / lane 1 encoded octet scrambled b9 / lane 2 encoded octet scrambled b9 / lane 3 All information provided in this document is subject to legal disclaimers. ...

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... NXP Semiconductors 10.3 Serial Peripheral Interface (SPI) 10.3.1 Protocol description The DAC1408D650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both Write mode and Read mode. ...

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... NXP Semiconductors 10.3.2 SPI timing description The SPI interface can operate at a frequency MHz. The SPI timing is shown in Figure 14. RESET_N SCS_N Fig 14. SPI timing diagram The SPI timing characteristics are given in Table 9. Symbol f SCLK t w(SCLK) t su(SCS_N) t h(SCS_N) t su(SDIO) t h(SDIO) t w(RESET_N) DAC1408D650 ...

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... NXP Semiconductors 10.4 Clock input The DAC1408D650 has one differential clock input, CLKINN/CLKINP. Fig 15. LVDS clock configuration Fig 16. Interfacing CML to LVDS The DAC1408D650 can operate with a clock frequency up to 312.5 MHz 650 MHz if the internal PLL is bypassed. The clock input can be LVDS (see it can also be interfaced with CML (see internal clock domain to another one is handled by Clock Domain Interface logic ...

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... NXP Semiconductors 10.5 FIR filters The three interpolation FIR filters have a stop band attenuation of at least 80 dBc and a pass band ripple of less than 0.0005 dB. Table 10. First interpolation filter Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) ...

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... NXP Semiconductors 10.6 Quadrature modulator and Numerically Controlled Oscillator (NCO) The quadrature modulator allows the 14-bit I and Q data to be mixed with the carrier signal generated by the NCO. The frequency of the NCO is programmed over 32 bits and the sign of the sine component can be inverted in order to operate positive or negative, lower or upper single sideband up-conversion ...

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... NXP Semiconductors Table 11. First interpolation filter Lower H(1) H(2) H(3) H(4) H(5) 10.8 DAC transfer function The full scale output current for each DAC is the sum of the two complementary current outputs   The output current depends on the digital input data: ...

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... NXP Semiconductors 10.9 Full-scale current 10.9.1 Regulation The DAC1408D650 reference circuitry integrates an internal band gap reference voltage which delivers a 1.25 V reference to the GAPOUT pin recommended to decouple pin GAPOUT using a 100 nF capacitor. The reference current is generated via an external resistor of 909  connected to pin VIRES ...

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... NXP Semiconductors Table 13. Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see “DAC_A_CFG_2 register (address 0Ah) bit (register 0Dh; see define the fine variation of the full-scale current (see Table 14. Default settings are shown highlighted. DAC_GAIN_FINE[5:0] Decimal  ...

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... NXP Semiconductors (register 0Ch; see register 0Eh; see the range of variation of the digital offset (see Table 15. Default settings are shown highlighted. DAC_OFFSET[11:0] Decimal 2048 2047 ...  ... +2046 +2047 10.11 Analog output The DAC1408D650 has two output channels each of which produces two complementary current outputs ...

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... NXP Semiconductors 10.12 Auxiliary DACs The DAC1408D650 integrates two auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a 10-bit resolution and are current sources (referenced to ground). I  ...

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... NXP Semiconductors 10.13 Output configuration 10.13.1 Basic output configuration The use of a differentially-coupled transformer output provides optimum distortion performance (see electrical isolation. Fig 19 The DAC1408D650 can operate configuration recommended to connect the center tap of the transformer  resistor connected to the 3.3 V analog power supply in order to adjust the DC common-mode to approximately 2 ...

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... NXP Semiconductors 10.13.2 DC interface to an Analog Quadrature Modulator (AQM) When the system operation requires to keep the DC component of the spectrum, the DAC1408D650 must use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC ...

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... NXP Semiconductors Figure 1.7 V when using the auxiliary DACs. i(cm) Fig 23. Example interface connection to an AQM with a V Figure 3.3 V when using the auxiliary DACs. i(cm) Fig 24. Example interface connection to an AQM with a V The constraints to adjusting the interface are the output compliance range of the DAC and the auxiliary DACs, the input common-mode level of the AQM, and the range of offset correction ...

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... NXP Semiconductors 10.13.3 AC interface to an Analog Quadrature Modulator (AQM) When the AQM common mode voltage is close to ground, the DAC1408D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 25 with a common-mode input level (V Fig 25. Example interface connection to an AQM with a V ...

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... NXP Semiconductors 10.13.4 Phase correction The Analog Quadrature Modulator which follows the DACs may have a phase imbalance which results in undesired sidebands. By adjusting the phase between the I and Q channels, the spur can be reduced. Without compensation the I and Q have a phase difference of  (90). The registers PHASECORR_CNTRL0 and PHASECORR_CNTRL1 located in register page 0 allow a phase variation from 75.7 ...

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Page 0 allocation map description Table 17. Page 0 register allocation map Address Register name R/W Bit definition b7 0 00h COMMON R/W SPI_3W 1 01h TXCFG R/W NCO_EN 2 02h PLLCFG R/W PLL_PD 3 03h FREQNCO_LSB R/W 4 ...

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Table 17. Page 0 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch DAC_B_AUX_MSB R/W 29 1Dh DAC_B_AUX_LSB R/W AUX_B_PD 31 1Fh PAGE_ADDRESS R AUX_B[9: ...

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... NXP Semiconductors 10.15.2.2 Page 0 bit definition detailed description Please refer to values emphasized in bold are the default values. Table 18. COMMON register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 7 SPI_3W 6 SPI_RST PD_ALL 0 GAP_PD Table 19. TXCFG register (address 01h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 19. TXCFG register (address 01h) bit description Default settings are shown highlighted. Bit Symbol INT_FIR[1:0] Table 20. PLLCFG register (address 02h) bit description Default settings are shown highlighted. Bit Symbol 7 PLL_PD PLL_DIV[1: PLL_PHASE[1:0] 0 PLL_POL Table 21. FREQNCO_LSB register (address 03h) bit description ...

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... NXP Semiconductors Table 24. FREQNCO_MSB register (address 06h) bit description Bit Symbol FREQ_NCO[31:24] Table 25. PHINCO_LSB register (address 07h) bit description Bit Symbol PH_NCO[7:0] Table 26. PHINCO_MSB register (address 08h) bit description Bit Symbol PH_NCO[15:8] Table 27. DAC_A_CFG_1 register (address 09h) bit description Default settings are shown highlighted. ...

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... NXP Semiconductors Table 30. DAC_B_CFG_1 register (address 0Ch) bit description Default settings are shown highlighted. Bit Symbol 7 DAC_B_PD 6 DAC_B_SLEEP DAC_B_OFFSET[5:0] Table 31. DAC_B_CFG_2 register (address 0Dh) bit description Bit Symbol DAC_B_GAIN_COARSE[1: DAC_B_GAIN_FINE[5:0] Table 32. DAC_B_CFG_3 register (address 0Eh) bit description Bit Symbol DAC_B_GAIN_COARSE[3: DAC_B_OFFSET[11:6] Table 33 ...

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... NXP Semiconductors Table 36. DAC_CURRENT_2 register (address 13h) bit description Default settings are shown highlighted. Bit Symbol DAC_DRV_BIAS[2: DAC_SLV_BIAS[2:0] Table 37. DAC_CURRENT_3 register (address 14h) bit description Default settings are shown highlighted. Bit Symbol DAC_CK_BIAS[2: DAC_CAS_BIAS[2:0] Table 38. DAC_SEL_PH_FINE register (address 15h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 44. DAC_B_AUX_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit Symbol 7 AUX_B_PD AUX_B[1:0] Table 45. DAC_B_AUX_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit Symbol PAGE[2:0] Table 46. Default settings are shown highlighted. BIAS[2:0] 000 ...

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Page 1 allocation map description Table 47. Page 1 register allocation map Address Register name R/W Bit definition b7 0 00h MDS_MAIN R/W MDS_EQCHECK[1:0] 1 01h MDS_WIN_PERIOD_A R/W 2 02h MDS_WIN_PERIOD_B R/W 3 03h MDS_MISCCNTRL0 R 04h ...

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... NXP Semiconductors 10.15.2.4 Page 1 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 48. MDS_MAIN register (address 00h) bit description Default settings are shown highlighted. Bit Symbol MDS_EQCHECK[1:0] 5 MDS_RUN 4 MDS_NCO 3 MDS_SEL_LN23 2 MDS_32T_ENA 1 MDS_MASTER 0 MDS_ENA Table 49 ...

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... NXP Semiconductors Table 51. MDS_MISCCNTRL0 register (address 03h) bit description Default settings are shown highlighted. Bit Symbol 4 MDS_EVAL_ENA 3 MDS_PRERUN_ENA MDS_PULSEWIDTH[2:0] Table 52. MDS_MAN_ADJUSTDLY register (address 04h) bit description Default settings are shown highlighted. Bit Symbol 7 MDS_MAN MDS_MAN_ADJUSTDLY[6:0] Table 53. MDS_AUTO_CYCLES register (address 05h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 54. MDS_MISCCNTRL1 register (address 06h) bit description Default settings are shown highlighted. Bit Symbol 4 MDS_RELOCK MDS_LOCK_DELAY[3:0] Table 55. MDS_ADJDELAY register (address 08h) bit description Default settings are shown highlighted. Bit Symbol MDS_ADJDELAY[6:0] Table 56. MDS_STATUS0 register (address 09h) bit description Default settings are shown highlighted. ...

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... NXP Semiconductors Table 57. MDS_STATUS1 register (address 0Ah) bit description Default settings are shown highlighted. Bit Symbol 3 JD_ODD 2 MDS_PRERUN 1 MDS_LOCKOUT 0 MDS_LOCK Table 58. PAGE_ADDRESS register (address 1Fh) bit description Default settings are shown highlighted. Bit Symbol PAGE[2:0] DAC1408D650 Product data sheet 2, 4 or 8 interpolating DAC with JESD204A ...

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Page 2 allocation map description Table 59. Page 2 register allocation map Address Register name R/W Bit definition b7 0 00h MAINCONTROL R 03h JCLK_CNTRL R/W SR_CDI 4 04h RST_EXT_FCLK R/W 5 05h RST_EXT_DCLK R/W 6 06h ...

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... NXP Semiconductors 10.15.2.6 Page 2 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 60. MAINCONTROL register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 5 FULL_RE_INIT 4 SYNC_INIT_LEVEL FORCE_RESET_DCLK 0 FORCE_RESET_FCLK Table 61. JCLK_CNTRL register (address 03h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 62. RST_EXT_FCLK register (address 04h) bit description Default settings are shown highlighted. Bit Symbol RST_EXT_FCLK_TIME[7:0] Table 63. RST_EXT_DCLK register (address 05h) bit description Default settings are shown highlighted. Bit Symbol RST_EXT_DCLK_TIME[7:0] Table 64. DCSMU_PREDIVCNT register (address 06h) bit description Default settings are shown highlighted. ...

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... NXP Semiconductors Table 70. TYPE_ID register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol 7 DAC FRONTEND [1:0] 4 DUAL DSP BIT_RES[1:0] Table 71. DAC_VERSION register (address 1Ch) bit description Default settings are shown highlighted. Bit Symbol DAC_VERSION_ID[7:0] Table 72. DIG_VERSION register (address 1Dh) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 75. Register 16h: SET_VCM_VOLTAGE Decimal Table 76. Register 17h: SET_SYNC Decimal Table 77. Register 17h: SET_SYNC Decimal DAC1408D650 Product data sheet 2, 4 or 8 interpolating DAC with JESD204A Lane common-mode voltage adjustment SET_VCM_VOLTAGE 1111 1110 1101 1100 1011 1010 1001 ...

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Page 4 allocation map description Table 78. Page 4 register allocation map Address Register name R/W Bit definition 00h SR_DLP_0 R/W SR_SWA_ SR_SWA_ LN3 1 01h SR_DLP_1 R/W SR_CNTRL SR_CNTRL _LN3 2 02h FORCE_LOCK R/W FORCE_ ...

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Table 78. Page 4 register allocation map …continued Address Register name R/W Bit definition 12h INIT_SCR_ R/W - S7T1_LN0 19 13h INIT_SCR_ R/W S15T8_LN1 20 14h INIT_SCR_ R/W - S7T1_LN1 21 15h INIT_SCR_ R/W S15T8_LN2 22 16h ...

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... NXP Semiconductors 10.15.2.8 Page 4 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 79. SR_DLP_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol 7 SR_SWA_LN3 6 SR_SWA_LN2 5 SR_SWA_LN1 4 SR_SWA_LN0 3 SR_CA_LN3 2 SR_CA_LN2 1 SR_CA_LN1 ...

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... NXP Semiconductors Table 81. FORCE_LOCK register (address 02h) bit description Default settings are shown highlighted. Bit Symbol 0 SR_ILA Table 82. MAN_LOCK_LN_1_0 register (address 03h) bit description Default settings are shown highlighted. Bit Symbol MAN_LOCK_LN1[3: MAN_LOCK_LN0[3:0] Table 83. MAN_LOCK_2_0 register (address 04h) bit description Default settings are shown highlighted. ...

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... NXP Semiconductors Table 84. CA_CNTRL register (address 05h) bit description Bit Symbol 1 SELECT_RF_F10_LN1 0 SELECT_RF_F10_LN0 Table 85. SCR_CNTRL register (address 06h) bit description Bit Symbol 7 MAN_SCR_LN3 6 MAN_SCR_LN2 5 MAN_SCR_LN1 4 MAN_SCR_LN0 3 FORCE_SCR_LN3 2 FORCE_SCR_LN2 1 FORCE_SCR_LN1 0 FORCE_SCR_LN0 DAC1408D650 Product data sheet 2, 4 or 8 interpolating DAC with JESD204A … ...

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... NXP Semiconductors Table 86. ILA_CNTRL register (address 07h) bit description Bit Symbol 7 SEL_421_211 SEL_ILA[1: SEL_LOCK[2:0] 1 SUP_LANE_SYN 0 EN_SCR Table 87. FORCE_ALIGN register (address 08h) bit description Bit Symbol 1 DYN_ALIGN_ENA 0 FORCE_ALIGN Table 88. MAN_ALIGN_LN_0_1 register (address 09h) bit description Bit Symbol MAN_ALIGN_LN1[3: MAN_ALIGN_LN0[3:0] DAC1408D650 Product data sheet 2 ...

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... NXP Semiconductors Table 89. MAN_ALIGN_LN_2_3 register (address 0Ah) bit description Bit Symbol MAN_ALIGN_LN3[3: MAN_ALIGN_LN2[3:0] Table 90. FA_ERR_HANDLING register (address 0Bh) bit description Default settings are shown highlighted. Bit Symbol SEL_KOUT_ UNEXP_LN23[1: SEL_KOUT_ UNEXP_LN10[1: SEL_NIT_ERR_ LN23[1: SEL_NIT_ERR_ LN10[1:0] DAC1408D650 Product data sheet 2, 4 or 8 interpolating DAC with JESD204A ...

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... NXP Semiconductors Table 91. SYNCOUT_MODE register (address 0Ch) bit description Default settings are shown highlighted. Bit Symbol SEL_RE_INIT[2:0] 4 SYNC_POL SEL_SYNC[3:0] Table 92. LANE_POLARITY register (address 0Dh) bit description Bit Symbol 3 POL_LN3 2 POL_LN2 1 POL_LN1 0 POL_LN0 DAC1408D650 Product data sheet 2, 4 or 8 interpolating DAC with JESD204A ...

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... NXP Semiconductors Table 93. LANE_SELECT register (address 0Eh) bit description Default settings are shown highlighted. Bit Symbol LANE_SEL_LN3[1: LANE_SEL_LN2[1: LANE_SEL_LN1[1: LANE_SEL_LN0[1:0] Table 94. SOFT_RESET_SCRAMBLER register (address 10h) bit description Bit Symbol 3 SR_SCR_LN3 2 SR_SCR_LN2 1 SR_SCR_LN1 0 SR_SCR_LN0 Table 95. INIT_SCR_S15T8_LN0 register (address 11h) bit description Bit ...

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... NXP Semiconductors Table 96. INIT_SCR_S7T1_LN0 (address 12h) bit description Bit Symbol INIT_VALUE_S7_S1_LN0[6:0] Table 97. INIT_SCR_S15T8_LN1 register (address 13h) bit description Bit Symbol INIT_VALUE_S15_S8_LN1[7:0] Table 98. INIT_SCR_S7T1_LN1 register (address 14h) bit description Bit Symbol INIT_VALUE_S7_S1_LN1[6:0] Table 99. INIT_SCR_S15T8_LN2 register (address 15h) bit description Bit Symbol INIT_VALUE_S15_S8_LN2[7:0] Table 100 ...

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... NXP Semiconductors Table 105. ERROR_HANDLING register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol 6 NAD_ERR_CORR 5 KUX_CORR 4 NAD_CORR CORR_MODE[1:0] 1 IMPL_ALT 0 IGNORE_ERR Table 106. REINIT_CNTRL register (address 1Ch) bit description Default settings are shown highlighted. Bit Symbol 7 REINIT_ILA_LN3 6 REINIT_ILA_LN2 5 REINIT_ILA_LN1 ...

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... NXP Semiconductors Table 106. REINIT_CNTRL register (address 1Ch) bit description Default settings are shown highlighted. Bit Symbol 3 RESYNC_O_L_LN3 2 RESYNC_O_L_LN2 1 RESYNC_O_L_LN1 0 RESYNC_O_L_LN0 Table 107. PAGE_ADDRESS register (address 1Fh) bit description Bit Symbol PAGE[2:0] DAC1408D650 Product data sheet 2, 4 or 8 interpolating DAC with JESD204A … ...

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Page 5 allocation map description Table 108. Page 5 register allocation map Address Register name R/W Bit definition 00h ILA_MON_1_0 R 1 01h ILA_MON_3_2 R 2 02h ILA_BUF_ERR 03h CA_MON R CA_MON_LN3[1:0] 4 ...

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Table 108. Page 5 register allocation map …continued Address Register name R/W Bit definition 11h FLAG_CNT_ R MSB_LN0 18 12h FLAG_CNT_LSB R _LN1 19 13h FLAG_CNT_ R MSB_LN1 20 14h FLAG_CNT_LSB R _LN2 21 15h FLAG_CNT_ R ...

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... NXP Semiconductors 10.15.2.10 Page 5 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 109. ILA_MON_1_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol ILA_MON_LN1[3: ILA_MON_LN0[3:0] Table 110. ILA_MON_3_2 register (address 01h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 113. DEC_FLAGS register (address 04h) bit description Bit Symbol 7 DEC_NIT_ERR_LN3 6 DEC_NIT_ERR_LN2 5 DEC_NIT_ERR_LN1 4 DEC_NIT_ERR_LN0 3 DEC_DISP_ERR_LN3 2 DEC_DISP_ERR_LN2 1 DEC_DISP_ERR_LN1 0 DEC_DISP_ERR_LN0 Table 114. KOUT_FLAG register (address 05h) bit description Bit Symbol 3 DEC_KOUT_LN3 2 DEC_KOUT_LN2 1 DEC_KOUT_LN1 0 DEC_KOUT_LN0 Table 115. K28_LN0_FLAG register (address 06h) bit description ...

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... NXP Semiconductors Table 118. K28_LN3_FLAG register (address 09h) bit description Bit Symbol 4 K28_7_LN3 3 K28_5_LN3 2 K28_4_LN3 1 K28_3_LN3 0 K28_0_LN3 Table 119. KOUT_UNEXPECTED_FLAG register (address 0Ah) bit description Bit Symbol 3 DEC_KOUT_UNEXP_LN3 2 DEC_KOUT_UNEXP_LN2 1 DEC_KOUT_UNEXP_LN1 0 DEC_KOUT_UNEXP_LN0 Table 120. LOCK_CNT_MON_LN01 register (address 0Bh) bit description Default settings are shown highlighted. ...

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... NXP Semiconductors Table 124. INTR_MISC_ENA register (address 0Fh) bit description Default settings are shown highlighted. Bit Symbol 7 INTR_ENA_CS_INIT_LN3 6 INTR_ENA_CS_INIT_LN2 5 INTR_ENA_CS_INIT_LN1 4 INTR_ENA_CS_INIT_LN0 3 INTR_ENA_BUF_ERR_LN3 2 INTR_ENA_BUF_ERR_LN2 1 INTR_ENA_BUF_ERR_LN1 0 INTR_ENA_BUF_ERR_LN0 Table 125. FLAG_CNT_LSB_LN0 register (address 10h) bit description Default settings are shown highlighted. Bit Symbol FLAG_CNT_LN0[7:0] Table 126 ...

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... NXP Semiconductors Table 132. FLAG_CNT_MSB_LN3 register (address 17h) bit description Default settings are shown highlighted. Bit Symbol FLAG_CNT_LN3[15:8] Table 133. BER_LEVEL_LSB register (address 18h) bit description Default settings are shown highlighted. Bit Symbol BER_LEVEL[7:0] Table 134. BER_LEVEL_MSB register (address 19h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 136. CNTRL_FLAGCNT_LN01 register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol 7 RST_CFC_LN1 SEL_CFC_LN1[2:0] 3 RST_CFC_LN0 SEL_CFC_LN0[2:0] Table 137. CNTRL_FLAGCNT_LN23 register (address 1Ch) bit description Default settings are shown highlighted. Bit Symbol 7 RST_CFC_LN3 SEL_CFC_LN3[2:0] 3 RST_CFC_LN2 SEL_CFC_LN2[2:0] Table 138. MON_FLAGS_RESET register (address 1Dh) bit description ...

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... NXP Semiconductors Table 139. DBG_CNTRL register (address 1Eh) bit description Bit Symbol 7 BER_MODE 6 INTR_CLEAR INTR_MODE[2:0] Table 140. PAGE_ADDRESS register (address 1Fh) bit description Bit Symbol PAGE[2:0] Table 141. Counter source Default settings are shown highlighted. SEL_CFC_LNn[2:0] 000 001 010 011 100 ...

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Page 6 allocation map description Table 143. Page 6 register allocation map Address Register name R/W Bit definition b7 0 00h LN0_CFG_0 R 1 01h LN0_CFG_1 02h LN0_CFG_2 03h LN0_CFG_3 R LN0_SCR 4 ...

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Table 143. Page 6 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN1_CFG_12 R 29 1Dh LN1_CFG_13 R 31 1Fh PAGE_ADDRESS R undefined at power-up or after reset ...

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... NXP Semiconductors 10.15.2.12 Page 6 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 144. LN0_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol LN0_DID[7:0] Table 145. LN0_CFG_1 register (address 01h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 152. LN0_CFG_8 register (address 08h) bit description Default settings are shown highlighted. Bit Symbol LN0_N’[4:0] Table 153. LN0_CFG_9 register (address 09h) bit description Default settings are shown highlighted. Bit Symbol LN0_S[4:0] Table 154. LN0_CFG_10 register (address 0Ah) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 161. LN1_CFG_3 register (address 13h) bit description Default settings are shown highlighted. Bit Symbol 7 LN1_SCR LN1_L[4:0] Table 162. LN1_CFG_4 register (address 14h) bit description Default settings are shown highlighted. Bit Symbol LN1_F[7:0] Table 163. LN1_CFG_5 register (address 15h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 169. LN1_CFG_11 register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol LN1_RES1[7:0] Table 170. LN1_CFG_12 register (address 1Ch) bit description Default settings are shown highlighted. Bit Symbol LN1_RES2[7:0] Table 171. LN1_CFG_13 register (address 1Dh) bit description Default settings are shown highlighted ...

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Page 7 allocation map description Table 173. Page 7 register allocation map Address Register name R/W Bit definition b7 0 00h LN2_CFG_0 R 1 01h LN2_CFG_1 02h LN2_CFG_2 03h LN2_CFG_3 R LN2_SCR 4 ...

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Table 173. Page 7 register allocation map …continued Address Register name R/W Bit definition b7 28 1Ch LN3_CFG_12 R 29 1Dh LN3_CFG_13 R 31 1Fh PAGE_ADDRESS R undefined at power-up or after reset ...

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... NXP Semiconductors 10.15.2.14 Page 7 bit definition detailed description Please refer to tables, all the values emphasized in bold are the default values. Table 174. LN2_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol LN2_DID[7:0] Table 175. LN2_CFG_1 register (address 01h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 182. LN2_CFG_8 register (address 08h) bit description Default settings are shown highlighted. Bit Symbol LN2_N'[4:0] Table 183. LN2_CFG_9 register (address 09h) bit description Default settings are shown highlighted. Bit Symbol LN2_S[4:0] Table 184. LN2_CFG_10 register (address 0Ah) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 191. LN3_CFG_3 register (address 13h) bit description Default settings are shown highlighted. Bit Symbol 7 LN3_SCR LN3_L[4:0] Table 192. LN3_CFG_4 register (address 14h) bit description Default settings are shown highlighted. Bit Symbol LN3_F[7:0] Table 193. LN3_CFG_5 register (address 15h) bit description Default settings are shown highlighted ...

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... NXP Semiconductors Table 199. LN3_CFG_11 register (address 1Bh) bit description Default settings are shown highlighted. Bit Symbol LN3_RES1[7:0] Table 200. LN3_CFG_12 register (address 1Ch) bit description Default settings are shown highlighted. Bit Symbol LN3_RES2[7:0] Table 201. LN3_CFG_13 register (address 1Dh) bit description Default settings are shown highlighted ...

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... NXP Semiconductors 11. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 0.85 mm terminal 1 index area terminal 1 64 index area Dimensions Unit max 1.00 0.05 0.30 mm nom 0.85 0.02 0.21 0.2 min 0.80 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

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... NXP Semiconductors 12. Abbreviations Table 203. Abbreviations Acronym AQM BER BW CDI CDMA CML CMOS DAC DCSMU DES EDGE FIR FPGA GSM IF ILA IMD3 LMDS LSB LTE LVDS MDS MMDS MSB NCO NMOS PLL SERDES SFDR SPI TD-SCDMA WCDMA WiMax DAC1408D650 Product data sheet 2 ...

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... NXP Semiconductors 13. Revision history Table 204. Revision history Document ID Release date DAC1408D650 v.4 20101126 • Modifications: Data sheet status changed from Preliminary to Product. • Text and drawings updated throughout entire data sheet. • Values in • Section 10.2.2 “Sync and word align” ...

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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

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... DAC with JESD204A NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

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... NXP Semiconductors 16. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 3. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 4. Thermal characteristics . . . . . . . . . . . . . . . . . . .6 Table 5. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 6. Digital Layer Processing Latency . . . . . . . . . . .12 Table 7. Read or Write mode access description . . . . .23 Table 8. Number of bytes to be transferred . . . . . . . . . .23 Table 9. SPI timing characteristics . . . . . . . . . . . . . . . .24 Table 10. Interpolation filter coefficients . . . . . . . . . . . . .26 Table 11 ...

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... NXP Semiconductors bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 59. Page 2 register allocation map . . . . . . . . . . . .51 Table 60. MAINCONTROL register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 61. JCLK_CNTRL register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 62. RST_EXT_FCLK register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 63. RST_EXT_DCLK register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 64. DCSMU_PREDIVCNT register (address 06h) bit description ...

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... NXP Semiconductors bit description . . . . . . . . . . . . . . . . . . . . . . . . .70 Table 113. DEC_FLAGS register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 114. KOUT_FLAG register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 115. K28_LN0_FLAG register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 116. K28_LN1_FLAG register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 117. K28_LN2_FLAG register (address 08h) bit description ...

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... NXP Semiconductors Table 165. LN1_CFG_7 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 166. LN1_CFG_8 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 167. LN1_CFG_9 register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 168. LN1_CFG_10 register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 Table 169. LN1_CFG_11 register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .82 Table 170 ...

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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 Application information 10.1 General description . . . . . . . . . . . . . . . . . . . . 11 10.2 JESD204A receiver . . . . . . . . . . . . . . . . . . . . 12 10 ...