HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 82
HSDC-JAKIT1W2/DB
Manufacturer Part Number
HSDC-JAKIT1W2/DB
Description
DAC/ADC LATTICE KIT
Manufacturer
NXP Semiconductors
Series
-r
Datasheets
1.ADC1413D125HNC15.pdf
(43 pages)
2.DAC1408D650HNC15.pdf
(98 pages)
3.HSDC-JAKIT1W2DB.pdf
(2 pages)
4.HSDC-JAKIT1W2DB.pdf
(2 pages)
5.HSDC-JAKIT1W2DB.pdf
(3 pages)
Specifications of HSDC-JAKIT1W2/DB
Main Purpose
Interface, ADC/DAC for Lattice ECP3 FPGA
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADC1413D, DAC1408D, ECP3 FPGA
Primary Attributes
Loop Back Demo with 2 High Speed Converters
Secondary Attributes
USB Powered
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6898
- ADC1413D125HNC15 PDF datasheet
- DAC1408D650HNC15 PDF datasheet #2
- HSDC-JAKIT1W2DB PDF datasheet #3
- HSDC-JAKIT1W2DB PDF datasheet #4
- HSDC-JAKIT1W2DB PDF datasheet #5
- Current page: 82 of 98
- Download datasheet (3Mb)
NXP Semiconductors
Table 169. LN1_CFG_11 register (address 1Bh) bit description
Default settings are shown highlighted.
Table 170. LN1_CFG_12 register (address 1Ch) bit description
Default settings are shown highlighted.
Table 171. LN1_CFG_13 register (address 1Dh) bit description
Default settings are shown highlighted.
Table 172. PAGE_ADDRESS register (address 1Fh) bit description
Default settings are shown highlighted.
DAC1408D650
Product data sheet
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
2 to 0
Symbol
LN1_RES1[7:0]
Symbol
LN1_RES2[7:0]
Symbol
LN1_FCHK[7:0]
Symbol
PAGE[2:0]
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R
Access
R
Access
R
Access
R/W
Value
-
Value
-
Value
Value
0h
-
2, 4 or 8 interpolating DAC with JESD204A
Description
lane 1 reserved field
Description
lane 1 reserved field
Description
Description
page_address
lane 1 checksum
DAC1408D650
© NXP B.V. 2010. All rights reserved.
82 of 98
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