HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 7

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
9. Characteristics
Table 5.
V
+85
maximum sample rate; PLL off unless otherwise specified.
DAC1408D650
Product data sheet
Symbol
V
V
V
I
I
I
I
P
Timing specifications
t
t
t
Clock inputs (CLKINN, CLKINP)
V
DDA(3V3)
DDD(1V8)
DDA(1V8)
d(startup)
d(restart)
lock
DDA(1V8)
DDA(3V3)
DDD(1V8)
DDA(1V8)
tot
i
DDD

C; typical values measured at V
= V
Characteristics
DDD
Parameter
analog supply voltage
(3.3 V)
digital supply voltage
(1.8 V)
analog supply voltage
(1.8 V)
analog supply current
(3.3 V)
digital supply current,
(1.8 V)
analog supply current,
(1.8 V)
digital supply current
difference
total power dissipation f
start-up delay time
restart delay time
lock time
input voltage
= 1.7 V to 1.9 V; V
[3]
DDA(3V3)
DDA(1V8)
Conditions
f
4 interpolation; NCO on
f
4 interpolation; NCO on
f
4 interpolation; NCO on
x/sin x function on;
f
4 interpolation; NCO off;
DAC Q off
f
4 interpolation; NCO off
f
4 interpolation; NCO on
f
2 interpolation; NCO off
f
2 interpolation; NCO on
Power-down mode;
f
4 interpolation; NCO on
from full Power-down mode
from Sleep mode
maximum input rate
range: CLK+ or CLK
V
o
o
o
s
s
s
s
s
s
o
All information provided in this document is subject to legal disclaimers.
gpd
= 640 Msps
= 640 Msps;
= 640 Msps;
= 640 Msps;
= 625 Msps;
= 625 Msps;
= 19 MHz; f
= 19 MHz; f
= 19 MHz; f
= 19 MHz; f
complete device;
Power-down mode
DAC A and DAC B;
Power-down mode
DAC A and DAC B;
Sleep mode
= 3.13 V to 3.47 V; AGND and GND are shorted together; T
= V
 < 50 mV
DDD
Rev. 4 — 26 November 2010
= 1.8 V; V
s
s
s
s
[4]
= 640 Msps;
= 640 Msps;
= 640 Msps;
= 640 Msps;
DDA(3V3)
2, 4 or 8 interpolating DAC with JESD204A
= 3.3 V; T
Test
I
I
I
I
I
I
I
C
C
C
C
C
I
I
I
C
[1]
[2]
amb
Min
3.13
1.7
1.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
825
= +25
DAC1408D650

C; R
Typ
3.3
1.8
1.8
42
354
412
52
0.82
1.26
1.51
1.33
1.51
0.04
0.62
0.83
20
300
11
-
L
= 50
3.47
Max
1.9
1.9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1575

© NXP B.V. 2010. All rights reserved.
amb
; I
O(fs)
=

40
= 20 mA;

Unit
V
V
V
mA
mA
mA
mA
W
W
W
W
W
W
W
W
ms
ns
s
mV
C to
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