HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 19

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
DAC1408D650
Product data sheet
The worst case clock skew is given by
The minimum allowable trace delay for the MDS signal is given by
In real applications, the master DAC can be anywhere and both conditions must be
satisfied:
Example:
 200 ps + 80 ps < t
 280 ps < t
 4.2 cm < L
Fig 10. Clock skew case 2: Master is closest
•
•
•
•
clock generator skew =  80 ps
FR4 substrate  15 cm/ns delay
clock trace length difference = 3 cm and 4 cm
Output sampling rate = 650 Msps
t
2

mds
slave 1 clock
slave 2 clock
master clock
mds
t
All information provided in this document is subject to legal disclaimers.
ref clock
mds
< 17.8 cm
< 1192 ps

Rev. 4 — 26 November 2010
mds
TDAC t
< 1538 ps  (266 ps + 80 ps)
–
1
.
PH01
PH02
t
PH03
2, 4 or 8 interpolating DAC with JESD204A
2
TDAC
=
PH03 PH01
–
DAC1408D650
.
t
001aal071
=
© NXP B.V. 2010. All rights reserved.
t
2
.
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