HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 60

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 84.
Table 85.
DAC1408D650
Product data sheet
Bit
1
0
Bit
7
6
5
4
3
2
1
0
Symbol
SELECT_RF_F10_LN1
SELECT_RF_F10_LN0
Symbol
MAN_SCR_LN3
MAN_SCR_LN2
MAN_SCR_LN1
MAN_SCR_LN0
FORCE_SCR_LN3
FORCE_SCR_LN2
FORCE_SCR_LN1
FORCE_SCR_LN0
CA_CNTRL register (address 05h) bit description
SCR_CNTRL register (address 06h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
1
0
1
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
…continued
2, 4 or 8 interpolating DAC with JESD204A
Description
Description
lane 3 manual scrambling
lane 2 manual scrambling
lane 1 manual scrambling
lane 0 manual scrambling
lane 3 scrambling mode
lane 2 scrambling mode
lane 1 sampling mode
lane 0 sampling mode
lane 1 scrambling mode
lane 0 scrambling mode
din_ca_ln1 sampled at falling edge f10_ln1
din_ca_ln1 sampled at rising edge f10_ln1
din_ca_ln0 sampled at falling edge f10_ln0
din_ca_ln0 sampled at rising edge f10_ln0
scrambling lane 3 off (when force_scr_ln3 = 1)
scrambling lane 3 on (when force_scr_ln3 = 1)
scrambling lane 2 off (when force_scr_ln2 = 1)
scrambling lane 2 on (when force_scr_ln2 = 1)
scrambling lane 1 off (when force_scr_ln1 = 1)
scrambling lane 1 on (when force_scr_ln1 = 1)
scrambling lane 0 off (when force_scr_ln0 = 1)
scrambling lane 0 on (when force_scr_ln0 = 1)
scrambling lane 3 depends on lock_ln3 and
en_scr
scrambling lane 3 depends on man_scr_ln3
scrambling lane 2 depends on lock_ln2 and
en_scr
scrambling lane 2 depends on man_scr_ln2
scrambling lane 1 depends on lock_ln1 and
en_scr
scrambling lane 1 depends on man_scr_ln1
scrambling lane 0 depends on lock_ln0 and
en_scr
scrambling lane 0 depends on man_scr_ln0
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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