HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 64

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 93.
Default settings are shown highlighted.
Table 94.
Table 95.
DAC1408D650
Product data sheet
Bit
7 to 6
5 to 4
3 to 2
1 to 0
Bit
3
2
1
0
Bit
7 to 0
Symbol
LANE_SEL_LN3[1:0]
LANE_SEL_LN2[1:0]
LANE_SEL_LN1[1:0]
LANE_SEL_LN0[1:0]
Symbol
SR_SCR_LN3
SR_SCR_LN2
SR_SCR_LN1
SR_SCR_LN0
Symbol
INIT_VALUE_S15_S8_LN0[7:0]
LANE_SELECT register (address 0Eh) bit description
SOFT_RESET_SCRAMBLER register (address 10h) bit description
INIT_SCR_S15T8_LN0 register (address 11h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Access
R/W
Value
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Value
0
1
0
1
0
1
0
1
Value
00h
2, 4 or 8 interpolating DAC with JESD204A
Description
lane 3 data mapping
lane 2 data mapping
lane 1 data mapping
lane 0 data mapping
Description
Description
initialization value for lane 0 descrambler bits
s15 : s8
lane 3 scrambler reset
lane 2 scrambler reset
lane 1 scrambler reset
lane 0 scrambler reset
ila_in_ln3 = lane_ln0 (dout and controls)
ila_in_ln3 = lane_ln1 (dout and controls)
ila_in_ln3 = lane_ln2 (dout and controls)
ila_in_ln3 = lane_ln3 (dout and controls)
ila_in_ln2 = lane_ln0 (dout and controls)
ila_in_ln2 = lane_ln1 (dout and controls)
ila_in_ln2 = lane_ln2 (dout and controls)
ila_in_ln2 = lane_ln3 (dout and controls)
ila_in_ln1 = lane_ln0 (dout and controls)
ila_in_ln1 = lane_ln1 (dout and controls)
ila_in_ln1 = lane_ln2 (dout and controls)
ila_in_ln1 = lane_ln3 (dout and controls
ila_in_ln0 = lane_ln0 (dout and controls)
ila_in_ln0 = lane_ln1 (dout and controls)
ila_in_ln0 = lane_ln2 (dout and controls)
ila_in_ln0 = lane_ln3 (dout and controls)
no action
soft_reset scrambler of lane 3
no action
soft_reset scrambler of lane 2
no action
soft_reset scrambler of lane 1
no action
soft_reset scrambler of lane 0
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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